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<p>Functions and defines to create and manipulate instruction operands.  
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Macros</h2></td></tr>
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<tr class="memitem:a9363b56a0e50b22fb2a55dc2af223c87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a9363b56a0e50b22fb2a55dc2af223c87">DR_REG_STOP_SEGMENT</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aba960c773accc850f5e245bcf69675fb">DR_SEG_GS</a></td></tr>
<tr class="memitem:ac0ce8f7566d47fde61f419bcf9ac8b6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ac0ce8f7566d47fde61f419bcf9ac8b6f">DR_REG_START_DR</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a12afd3e4492a8046aeef1f1ba5479f95">DR_REG_DR0</a></td></tr>
<tr class="memitem:a078578a811b8f67166a0d26548468697"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a078578a811b8f67166a0d26548468697">DR_REG_STOP_DR</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a89f29c7ce774f35ab307a2dcec374133">DR_REG_DR15</a></td></tr>
<tr class="memitem:a118f2c0b8b2ef31ff3cfce8bf43ad082"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a118f2c0b8b2ef31ff3cfce8bf43ad082">DR_REG_START_CR</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a3b6b6f92a247b1bfb3eb8129275211c5">DR_REG_CR0</a></td></tr>
<tr class="memitem:a3166c9f50c00c403f13e0025d843e85b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a3166c9f50c00c403f13e0025d843e85b">DR_REG_STOP_CR</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a8a3a826c39b63ee447c7ebc46fcd0a64">DR_REG_CR15</a></td></tr>
<tr class="memitem:a13480b2d07fe53c9292ffaacedcf7231"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a13480b2d07fe53c9292ffaacedcf7231">DR_REG_LAST_VALID_ENUM</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a30d681f080672754d59e4c92eb8110e3">DR_REG_YMM15</a></td></tr>
<tr class="memitem:af01db24b9e2a038656f90f1d5230c098"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#af01db24b9e2a038656f90f1d5230c098">DR_REG_LAST_ENUM</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a30d681f080672754d59e4c92eb8110e3">DR_REG_YMM15</a></td></tr>
<tr class="memitem:a992970f92f717142180ea31fe5eb2493"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a992970f92f717142180ea31fe5eb2493">OPSZ_PTR</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a066a3d6699a61167eb0ba00e529c2e41">OPSZ_8</a></td></tr>
<tr class="memitem:af11e428cd2f68de6cb185384a8fd9713"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#af11e428cd2f68de6cb185384a8fd9713">OPSZ_STACK</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a066a3d6699a61167eb0ba00e529c2e41">OPSZ_8</a></td></tr>
<tr class="memitem:a0cda7955a0d28b070a3fc522d9755323"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a0cda7955a0d28b070a3fc522d9755323">OPSZ_VARSTACK</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a0119f9bdffad99695b3c2ba9e7588dd5">OPSZ_4x8_short2</a></td></tr>
<tr class="memitem:a7398a217ece979ba30b193b2aa3f4e3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a7398a217ece979ba30b193b2aa3f4e3c">OPSZ_ret</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aec5f3627d823c5158599a01e54cc6668">OPSZ_4x8_short2xi8</a></td></tr>
<tr class="memitem:a505a5cc55d07df68642a384bff1311fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a505a5cc55d07df68642a384bff1311fd">OPSZ_call</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a7398a217ece979ba30b193b2aa3f4e3c">OPSZ_ret</a></td></tr>
<tr class="memitem:abe0304f622362c52b450f86fb3d135b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#abe0304f622362c52b450f86fb3d135b5">OPSZ_lea</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a5ca16ff95c562237f969f3f1578da995">OPSZ_0</a></td></tr>
<tr class="memitem:ae4cbcae74f1e1c4e3b3e4c3a9daac175"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ae4cbcae74f1e1c4e3b3e4c3a9daac175">OPSZ_invlpg</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a5ca16ff95c562237f969f3f1578da995">OPSZ_0</a></td></tr>
<tr class="memitem:a6b138a841e72eb3c8340d9aaa16332f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a6b138a841e72eb3c8340d9aaa16332f5">OPSZ_xlat</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a1ae7577a8e73d4a38aa18598de9ba8a6">OPSZ_1</a></td></tr>
<tr class="memitem:a7af1cd71dcdc12ee0bd882e0e632770d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a7af1cd71dcdc12ee0bd882e0e632770d">OPSZ_clflush</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a1ae7577a8e73d4a38aa18598de9ba8a6">OPSZ_1</a></td></tr>
<tr class="memitem:a32ac28899da38ae6198e50ac9a9e1c51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a32ac28899da38ae6198e50ac9a9e1c51">OPSZ_prefetch</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a1ae7577a8e73d4a38aa18598de9ba8a6">OPSZ_1</a></td></tr>
<tr class="memitem:ac00f6c2706be7498c21120cf9e721ae7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ac00f6c2706be7498c21120cf9e721ae7">OPSZ_lgdt</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a></td></tr>
<tr class="memitem:ac3b6d6486ae0825aad79fe1db73ed76b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ac3b6d6486ae0825aad79fe1db73ed76b">OPSZ_sgdt</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a></td></tr>
<tr class="memitem:a8ec03cb0036c517b23b553e4462f6456"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a8ec03cb0036c517b23b553e4462f6456">OPSZ_lidt</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a></td></tr>
<tr class="memitem:a380f205691106bd9d0a97d92bf13c157"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a380f205691106bd9d0a97d92bf13c157">OPSZ_sidt</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a></td></tr>
<tr class="memitem:afd7af2c97db706df54e93a703c8993d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#afd7af2c97db706df54e93a703c8993d8">OPSZ_bound</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a6b22b3dc31990898191d352a02bedb1f">OPSZ_8_short4</a></td></tr>
<tr class="memitem:ac1f1c7cdbfc99ad8700ec323e23daac4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ac1f1c7cdbfc99ad8700ec323e23daac4">OPSZ_maskmovq</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a066a3d6699a61167eb0ba00e529c2e41">OPSZ_8</a></td></tr>
<tr class="memitem:aed8168193c674869dee04d57b80b0152"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aed8168193c674869dee04d57b80b0152">OPSZ_maskmovdqu</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa1d772e6c9ef66ff48285c659bec3eca">OPSZ_16</a></td></tr>
<tr class="memitem:adfdb5621464efafd92c790be4910f792"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#adfdb5621464efafd92c790be4910f792">OPSZ_fldenv</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a26719c230384ea132717a65d29b037f2">OPSZ_28_short14</a></td></tr>
<tr class="memitem:a6df647fce51b5ca4cdc98542a06ae3f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a6df647fce51b5ca4cdc98542a06ae3f7">OPSZ_fnstenv</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a26719c230384ea132717a65d29b037f2">OPSZ_28_short14</a></td></tr>
<tr class="memitem:ab13555485fd05378da3cf406d966240e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ab13555485fd05378da3cf406d966240e">OPSZ_fnsave</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa970ca06e8dc492d880cc8dd657b2f14">OPSZ_108_short94</a></td></tr>
<tr class="memitem:a5bbf389a2a87a9309ca87514c307fad9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a5bbf389a2a87a9309ca87514c307fad9">OPSZ_frstor</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa970ca06e8dc492d880cc8dd657b2f14">OPSZ_108_short94</a></td></tr>
<tr class="memitem:a47d9d260d6ec125ac308fe6a27efc7d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a47d9d260d6ec125ac308fe6a27efc7d2">OPSZ_fxsave</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a6ee100110eb7730aabf8762c7239a02f">OPSZ_512</a></td></tr>
<tr class="memitem:aa9f99ce71b7f6e2f66fc314650df0969"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aa9f99ce71b7f6e2f66fc314650df0969">OPSZ_fxrstor</a>&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a6ee100110eb7730aabf8762c7239a02f">OPSZ_512</a></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:a39fca1837c5ce7715cbf571669660c13"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom">{ <br/>
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<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aa5c51b561fd965d340d4cf6266d814b8">DR_REG_RAX</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aa05b6f262667c94bb6e6b1ef454a69b4">DR_REG_RCX</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13acf4384fb8af2fd2e6865ded40e131d5e">DR_REG_RDX</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a02092feb3b7da559059ee67eae67b257">DR_REG_RBX</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a79c4d3f4b50d5aa74aea84bf88eac7d0">DR_REG_RSP</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a2a7f8e7636bc2066a103cacc1171973f">DR_REG_RBP</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aa01a866894daa9e7f3716a05dd8f79fc">DR_REG_RSI</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a1a27364ae96a8795ddcd91239b9625bf">DR_REG_RDI</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a6ce9d564068bf72ec43d9162f2119c02">DR_REG_R8</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a47f7053ccf7bdaf5c778d2391883378d">DR_REG_R9</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a6047f7e372ce556998d7cb5817a7a5a1">DR_REG_R10</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a5a4e943d15f08c4ddc25fb0527b88c53">DR_REG_R11</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13ab872b0fafeb55817f21c95f80ef06c11">DR_REG_R12</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a5b6924937cf9882d7be7a56205ff25d4">DR_REG_R13</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a16927fccb2fc7be0a63645526d9ea793">DR_REG_R14</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13af40c522c9dc92ca3e127dc6c49c59a81">DR_REG_R15</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a58aa570736353c817f71fcc400a2d2dc">DR_REG_EAX</a>, 
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&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a5a09a75ede7ccefae6f8ff82bba5bae4">DR_REG_ECX</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13ab86ca7bcddcb447aaa3e42e54c294980">DR_REG_EDX</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a9c25504c9114d17fda24e07e2121e888">DR_REG_EBX</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aef7e5609d413862bbe58a43aa7868281">DR_REG_ESP</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a10f6ee04809e03dc6d15f5706eb7fff1">DR_REG_EBP</a>, 
<br/>
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&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aba7af08dcaafc2dbe3c98ba52cb1f3b2">DR_REG_CR2</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a21c3267961f5abb9ab5887f0bd70581d">DR_REG_CR3</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13ae2f361f257ca972ac1e02771d98cfc4e">DR_REG_CR4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13abb5ed4626f8c59bcaf3f42700a3d8fa2">DR_REG_CR5</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a33e5f8f41e4001147cbbdc991300a6d5">DR_REG_CR6</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a2bb88c4f1e662daa53dbd75b07c8895c">DR_REG_CR7</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a77bcc2c3a49a858d0b77118b89466412">DR_REG_CR8</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a103a98c7eb4d976fa117fed3578dfe81">DR_REG_CR9</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13af9a5ba2c19c637a69d5cf25f73e5d34f">DR_REG_CR10</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a6b654a966b48977c3687c2b24f7fe8ef">DR_REG_CR11</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a457d424c43f5a32b4e8ddc5e1344b086">DR_REG_CR12</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a7493f68f4c93f46b7a0032885b0701f4">DR_REG_CR13</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a7deb6444d23c983c69cd4067781d6be8">DR_REG_CR14</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a8a3a826c39b63ee447c7ebc46fcd0a64">DR_REG_CR15</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13af627e9b7e65af958771933dba270783b">DR_REG_INVALID</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a506c32e4da1e93ed469bee48d2746c36">DR_REG_YMM0</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13ac6bfad04cc3881630749998d37cc8b94">DR_REG_YMM1</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13ad6f63ec6b3fc6fd85b1f61fac5afea8c">DR_REG_YMM2</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a1c1e1c5da3d90aa0defada496eb8f5e8">DR_REG_YMM3</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13afce2a84d7b7296826a0015074d49a875">DR_REG_YMM4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13ab71fb800029282debea33210753b4a8a">DR_REG_YMM5</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a1ce86c2f2d9e753d50ad0d9ba38bdd15">DR_REG_YMM6</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13adc8ee6513706d60ce50ef527aa270896">DR_REG_YMM7</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a52c18153e2decc9e3197f7f35ca1a5fa">DR_REG_YMM8</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13ae7556ce24f531722623da3dedabf0cbb">DR_REG_YMM9</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a60f4862d1094ad97111a6dec83a59cd9">DR_REG_YMM10</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a636d90b537b7bc3359ad49469eab847f">DR_REG_YMM11</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13ad186d80221df365f693a5d5f10455d53">DR_REG_YMM12</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aae6c9c9daf4daa70b10637881e97c0c6">DR_REG_YMM13</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a60ab04ccb23565254ee97fffd83fe92e">DR_REG_YMM14</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a30d681f080672754d59e4c92eb8110e3">DR_REG_YMM15</a>
<br/>
 }</td></tr>
<tr class="memitem:aaf8fd5f0e57d456151c951e0f3715fc4"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom">{ <br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4ad8ebfb0c9725d4de8dc822fe6e0434a4">OPSZ_NA</a> =  DR_REG_INVALID+1
, <br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a5ca16ff95c562237f969f3f1578da995">OPSZ_0</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a1ae7577a8e73d4a38aa18598de9ba8a6">OPSZ_1</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a17ae2b57438dc78b74918634536ab8ec">OPSZ_2</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a0ccef0d75b3f473bf275388804c8b85c">OPSZ_4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a0bd061af35fa7349ae8f49f52c70d353">OPSZ_6</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a066a3d6699a61167eb0ba00e529c2e41">OPSZ_8</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4ad77bb391958eb41218d362142f19c071">OPSZ_10</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa1d772e6c9ef66ff48285c659bec3eca">OPSZ_16</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a518e12d87392b8b0fcb87bbc37d5e43d">OPSZ_14</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a3a1817fe7db80f134788fd82643f1aae">OPSZ_28</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a4a3e5ca13e5d2e4efedef6d5e1d4e79c">OPSZ_94</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a69e3b06a69484ded9cdc60bd0cdb37fe">OPSZ_108</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a6ee100110eb7730aabf8762c7239a02f">OPSZ_512</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a903faaf86532c743c799845eb11eff7e">OPSZ_2_short1</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a7b7c9306312252995d6e0634ee0a3caa">OPSZ_4_short2</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a32ada6d380c77e31381cbad6f2dd2718">OPSZ_4_rex8_short2</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4ad623004d7c3a3b723815c429c9cc0355">OPSZ_4_rex8</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa4d243486345db5568617b738388c0de">OPSZ_6_irex10_short4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4ab85e1e4770430376365d9ccdc4edbeef">OPSZ_8_short2</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a6b22b3dc31990898191d352a02bedb1f">OPSZ_8_short4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a26719c230384ea132717a65d29b037f2">OPSZ_28_short14</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa970ca06e8dc492d880cc8dd657b2f14">OPSZ_108_short94</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a9d969185f0b397e78c06ab0b45f07a00">OPSZ_4x8</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a0119f9bdffad99695b3c2ba9e7588dd5">OPSZ_4x8_short2</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aec5f3627d823c5158599a01e54cc6668">OPSZ_4x8_short2xi8</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a674723f76cae47df43261656d550b0b1">OPSZ_4_short2xi4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a01324b1c6672d657c931c192140a3c52">OPSZ_1_reg4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4ad4c71f8b85b6d29bfab5979cfe665e3d">OPSZ_2_reg4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4ac5ca3360d331fded45ee1cefbc6a7447">OPSZ_4_reg16</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4ab3abe67788f31af3804456b54ce4fe3f">OPSZ_xsave</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a4f9af8f5df4e4ad8a5790a96405c1ae8">OPSZ_12</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4abcfb8f7f5225a98205186f02ee24c25d">OPSZ_32</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aabba0c8aa7f8e2c7e6558a3067c958c4">OPSZ_40</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a0b33dc779b6e35a692933392845748d3">OPSZ_32_short16</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4abea75bfe53a3c81f12ebc38e382378aa">OPSZ_8_rex16</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4acf7f69fbb6d4eb3b898590fba55348b7">OPSZ_8_rex16_short4</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4af2ed43be9c2201e06c76a1b36f79920f">OPSZ_12_rex40_short6</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aeff79665bf0fa144556f2964a498bc94">OPSZ_16_vex32</a>, 
<br/>
&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a860c730e78eac07dc1b57377fad5887c">OPSZ_15</a>
<br/>
 }</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:aa073f62ac5b6664f9e8297fe05a1598e"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE <a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aa073f62ac5b6664f9e8297fe05a1598e">opnd_create_null</a> (void)</td></tr>
<tr class="memitem:a0714576ebc35cf7efe2855126ad716e1"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE <a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a0714576ebc35cf7efe2855126ad716e1">opnd_create_reg</a> (reg_id_t r)</td></tr>
<tr class="memitem:a321271ddce2b40d5a094aa22fdfdeb0b"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE <a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a321271ddce2b40d5a094aa22fdfdeb0b">opnd_create_reg_partial</a> (reg_id_t r, opnd_size_t subsize)</td></tr>
<tr class="memitem:a31d4ba093e7c07c9ed899bc2ac860981"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a31d4ba093e7c07c9ed899bc2ac860981">opnd_create_immed_int</a> (ptr_int_t i, opnd_size_t data_size)</td></tr>
<tr class="memitem:adaecf3f6163ecae61512cda47c5106fc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#adaecf3f6163ecae61512cda47c5106fc">opnd_create_immed_float</a> (float f)</td></tr>
<tr class="memitem:a182e9189189d6f8425a57b1bf87c7a4c"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE <a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a182e9189189d6f8425a57b1bf87c7a4c">opnd_create_pc</a> (app_pc pc)</td></tr>
<tr class="memitem:a19bcdbac872081a5c74285f078a14c59"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a19bcdbac872081a5c74285f078a14c59">opnd_create_far_pc</a> (ushort seg_selector, app_pc pc)</td></tr>
<tr class="memitem:af0e9e7e3f5a999615b7d5846fb731382"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#af0e9e7e3f5a999615b7d5846fb731382">opnd_create_instr</a> (<a class="el" href="structinstr__t.html">instr_t</a> *instr)</td></tr>
<tr class="memitem:a473c30663f325c09134371863f8f237a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a473c30663f325c09134371863f8f237a">opnd_create_instr_ex</a> (<a class="el" href="structinstr__t.html">instr_t</a> *instr, opnd_size_t size, ushort shift)</td></tr>
<tr class="memitem:a95f47d1d589d4a9566a581588fecaedf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a95f47d1d589d4a9566a581588fecaedf">opnd_create_far_instr</a> (ushort seg_selector, <a class="el" href="structinstr__t.html">instr_t</a> *instr)</td></tr>
<tr class="memitem:ae4a6e3dea7723c44dcacd9e16d47afd0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ae4a6e3dea7723c44dcacd9e16d47afd0">opnd_create_mem_instr</a> (<a class="el" href="structinstr__t.html">instr_t</a> *instr, short disp, opnd_size_t data_size)</td></tr>
<tr class="memitem:a009d49c1c9dec11da5b4f4b644bd9c72"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a009d49c1c9dec11da5b4f4b644bd9c72">opnd_create_base_disp</a> (reg_id_t base_reg, reg_id_t index_reg, int scale, int disp, opnd_size_t data_size)</td></tr>
<tr class="memitem:abc9e73f45c6691e79b61bcc33c6bec1e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#abc9e73f45c6691e79b61bcc33c6bec1e">opnd_create_base_disp_ex</a> (reg_id_t base_reg, reg_id_t index_reg, int scale, int disp, opnd_size_t size, bool encode_zero_disp, bool force_full_disp, bool disp_short_addr)</td></tr>
<tr class="memitem:ad40dc03947985fe2ce948377b3a630ce"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ad40dc03947985fe2ce948377b3a630ce">opnd_create_far_base_disp</a> (reg_id_t seg, reg_id_t base_reg, reg_id_t index_reg, int scale, int disp, opnd_size_t data_size)</td></tr>
<tr class="memitem:af6a76130e0562edc5f26cf0625de51b6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#af6a76130e0562edc5f26cf0625de51b6">opnd_create_far_base_disp_ex</a> (reg_id_t seg, reg_id_t base_reg, reg_id_t index_reg, int scale, int disp, opnd_size_t size, bool encode_zero_disp, bool force_full_disp, bool disp_short_addr)</td></tr>
<tr class="memitem:a6c4e5d5376ce4dc1ba7081119d97a16d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a6c4e5d5376ce4dc1ba7081119d97a16d">opnd_create_abs_addr</a> (void *addr, opnd_size_t data_size)</td></tr>
<tr class="memitem:a8716c716b3589b75e887a86f782433be"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a8716c716b3589b75e887a86f782433be">opnd_create_far_abs_addr</a> (reg_id_t seg, void *addr, opnd_size_t data_size)</td></tr>
<tr class="memitem:a429f69f7bc430cf278b5702818b25fcc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a429f69f7bc430cf278b5702818b25fcc">opnd_create_rel_addr</a> (void *addr, opnd_size_t data_size)</td></tr>
<tr class="memitem:a5378f9a33c968e32ac7ebc9acb8db3bb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a5378f9a33c968e32ac7ebc9acb8db3bb">opnd_create_far_rel_addr</a> (reg_id_t seg, void *addr, opnd_size_t data_size)</td></tr>
<tr class="memitem:ae9f59d1eb2315acac4e5c402d7c25cd0"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ae9f59d1eb2315acac4e5c402d7c25cd0">opnd_is_null</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a68c8e3f02a0617550c6b559f28d8ad25"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a68c8e3f02a0617550c6b559f28d8ad25">opnd_is_reg</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ad8e257fb364af0aed0c0be066d8d1da3"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ad8e257fb364af0aed0c0be066d8d1da3">opnd_is_reg_partial</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a29d3ae74efdf22d239d8c78f5ac4a760"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a29d3ae74efdf22d239d8c78f5ac4a760">opnd_is_immed</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a63ea2846af63ed4d9f1a21e2316919e1"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a63ea2846af63ed4d9f1a21e2316919e1">opnd_is_immed_int</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a1a0739be7d1db70d1f06b33fe609786b"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a1a0739be7d1db70d1f06b33fe609786b">opnd_is_immed_float</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:aab9a90569e9a9b1dc73a25d77d315291"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aab9a90569e9a9b1dc73a25d77d315291">opnd_is_pc</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ab057af1a3fe3f842de20e5f5200a6525"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ab057af1a3fe3f842de20e5f5200a6525">opnd_is_near_pc</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:abbe0b704c1a572caf9297c48b023f25e"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#abbe0b704c1a572caf9297c48b023f25e">opnd_is_far_pc</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:aa278662a54e9df9de5f06c30e53d7596"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aa278662a54e9df9de5f06c30e53d7596">opnd_is_instr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:aee97636116eb65baace7ccd74b8d1083"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aee97636116eb65baace7ccd74b8d1083">opnd_is_near_instr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a93533e9bd0ad51af0f0f8d10535a7b0e"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a93533e9bd0ad51af0f0f8d10535a7b0e">opnd_is_far_instr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ae0a71c34e19463d38a3a74f3a1ed5cc1"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ae0a71c34e19463d38a3a74f3a1ed5cc1">opnd_is_mem_instr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a6b359b6b460bfdaf00985505e54a5be4"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a6b359b6b460bfdaf00985505e54a5be4">opnd_is_base_disp</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a1895348ff69657c8cefb4cc49066cc76"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a1895348ff69657c8cefb4cc49066cc76">opnd_is_near_base_disp</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a7886f0e427bd5f51d479191d4a1fbb8d"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a7886f0e427bd5f51d479191d4a1fbb8d">opnd_is_far_base_disp</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:acdea9def1c35fc3e62d53dd0154aa8c4"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#acdea9def1c35fc3e62d53dd0154aa8c4">opnd_is_vsib</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a22bbf7d42f7ff2011970294e70176caf"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a22bbf7d42f7ff2011970294e70176caf">opnd_is_abs_addr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a7a28885abf6f2956429ab26f02c46cd2"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a7a28885abf6f2956429ab26f02c46cd2">opnd_is_near_abs_addr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a87cc8c62aeb4b7a50a40dd1ce13226d0"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a87cc8c62aeb4b7a50a40dd1ce13226d0">opnd_is_far_abs_addr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a17c7a1b3e5a6eecdfdb5bf69cdf2ecd4"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a17c7a1b3e5a6eecdfdb5bf69cdf2ecd4">opnd_is_rel_addr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ad32e874a224106f72dc50e8441752f3f"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ad32e874a224106f72dc50e8441752f3f">opnd_is_near_rel_addr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a3ee3109f51ef2301b3dc7a1a6b56a496"><td class="memItemLeft" align="right" valign="top">INSTR_INLINE bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a3ee3109f51ef2301b3dc7a1a6b56a496">opnd_is_far_rel_addr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a5ed7af0d7ea648245c8efd77b30d7e69"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a5ed7af0d7ea648245c8efd77b30d7e69">opnd_is_memory_reference</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ae5d037c6eb3d4fb3a8902d59b4660fd5"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ae5d037c6eb3d4fb3a8902d59b4660fd5">opnd_is_far_memory_reference</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a32811b9de9a29e3c915315aa2a2aaea7"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a32811b9de9a29e3c915315aa2a2aaea7">opnd_is_near_memory_reference</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:aafe34146e6477dae4976101656ff414c"><td class="memItemLeft" align="right" valign="top">opnd_size_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aafe34146e6477dae4976101656ff414c">opnd_get_size</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a0946a0be0d1f445e43a05e5f88e4936e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a0946a0be0d1f445e43a05e5f88e4936e">opnd_set_size</a> (<a class="el" href="structopnd__t.html">opnd_t</a> *opnd, opnd_size_t newsize)</td></tr>
<tr class="memitem:a8e4c0d56682446b190ca3a56d4005162"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a8e4c0d56682446b190ca3a56d4005162">opnd_get_reg</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a680178047906839124b347d91d64bfd4"><td class="memItemLeft" align="right" valign="top">ptr_int_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a680178047906839124b347d91d64bfd4">opnd_get_immed_int</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a89c61514befd2496743811e510ee88a4"><td class="memItemLeft" align="right" valign="top">float&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a89c61514befd2496743811e510ee88a4">opnd_get_immed_float</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a0f280a1c281a7300763cfd52b6f68a33"><td class="memItemLeft" align="right" valign="top">app_pc&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a0f280a1c281a7300763cfd52b6f68a33">opnd_get_pc</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:afa3b83a7842dcd6a12dc8bd8c2b36287"><td class="memItemLeft" align="right" valign="top">ushort&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#afa3b83a7842dcd6a12dc8bd8c2b36287">opnd_get_segment_selector</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a19f83082c18155cb0518578331817f19"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structinstr__t.html">instr_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a19f83082c18155cb0518578331817f19">opnd_get_instr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:aa15b1fcb0d983e84c95717d34f4ba223"><td class="memItemLeft" align="right" valign="top">ushort&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aa15b1fcb0d983e84c95717d34f4ba223">opnd_get_shift</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a1e7ea7b3b96e8d3ccc3c01e777a0ddfb"><td class="memItemLeft" align="right" valign="top">short&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a1e7ea7b3b96e8d3ccc3c01e777a0ddfb">opnd_get_mem_instr_disp</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a48898a22c401aef47d2fd029edd96255"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a48898a22c401aef47d2fd029edd96255">opnd_get_base</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a3603fa5bce569d9fe5d1e8c204926f26"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a3603fa5bce569d9fe5d1e8c204926f26">opnd_get_disp</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ad44ed441d6f51cd380eda3a4973d185b"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ad44ed441d6f51cd380eda3a4973d185b">opnd_is_disp_encode_zero</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a455f54825aca4ae0aafd4897aeacbfc4"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a455f54825aca4ae0aafd4897aeacbfc4">opnd_is_disp_force_full</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a2df86e4357068eb635b4861edc648524"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a2df86e4357068eb635b4861edc648524">opnd_is_disp_short_addr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a43fac395cee7b97ddd4243d2a7f9ab29"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a43fac395cee7b97ddd4243d2a7f9ab29">opnd_get_index</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:aa049384e6538ab85e1167fe81ea928a8"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aa049384e6538ab85e1167fe81ea928a8">opnd_get_scale</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ab71f1fc4767e5d30434b01d44a7bff44"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ab71f1fc4767e5d30434b01d44a7bff44">opnd_get_segment</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ace1b4d479d9260f74734d0d56c2e4e67"><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ace1b4d479d9260f74734d0d56c2e4e67">opnd_get_addr</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:aeb508e0926cc8bcba006da1e0bc8138b"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aeb508e0926cc8bcba006da1e0bc8138b">opnd_num_regs_used</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a5e506374ff3025564d197b3fcbcf7cb8"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a5e506374ff3025564d197b3fcbcf7cb8">opnd_get_reg_used</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd, int index)</td></tr>
<tr class="memitem:a4b412ff3d08026f65ac44e1c6659a58a"><td class="memItemLeft" align="right" valign="top">const char *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a4b412ff3d08026f65ac44e1c6659a58a">get_register_name</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a039805550c6039cfc2bb0f6359e93636"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a039805550c6039cfc2bb0f6359e93636">reg_32_to_16</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a7a4d6e463a49f281c72eee9a61d48613"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a7a4d6e463a49f281c72eee9a61d48613">reg_32_to_8</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a6d6aa6e0596070095845e0214c4a08e8"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a6d6aa6e0596070095845e0214c4a08e8">reg_32_to_64</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a887f5c54d733c30ceb6a943d9a9427db"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a887f5c54d733c30ceb6a943d9a9427db">reg_64_to_32</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a80fb7f17bae1dc1cf6b8a45a9a3b42a3"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a80fb7f17bae1dc1cf6b8a45a9a3b42a3">reg_is_extended</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a6166e576e7529c45ca857c624dc732e0"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a6166e576e7529c45ca857c624dc732e0">reg_32_to_opsz</a> (reg_id_t reg, opnd_size_t sz)</td></tr>
<tr class="memitem:adccf1dfd3ec95b71a8a0b205cf48da7a"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#adccf1dfd3ec95b71a8a0b205cf48da7a">reg_resize_to_opsz</a> (reg_id_t reg, opnd_size_t sz)</td></tr>
<tr class="memitem:ae895cb370884b8acc4cdfc523f1101df"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ae895cb370884b8acc4cdfc523f1101df">reg_parameter_num</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a4780b2b04fe82ec06dc481d48cbbf6e5"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a4780b2b04fe82ec06dc481d48cbbf6e5">reg_is_gpr</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a2a1c2869e0ff18940bfdbbd9e8771fb4"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a2a1c2869e0ff18940bfdbbd9e8771fb4">reg_is_segment</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a3e0e2b3f3e6ed53ac71a478230ef3ea7"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a3e0e2b3f3e6ed53ac71a478230ef3ea7">reg_is_xmm</a> (reg_id_t reg)</td></tr>
<tr class="memitem:ab36ef1d2d054727c31f46c2d768fd476"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ab36ef1d2d054727c31f46c2d768fd476">reg_is_ymm</a> (reg_id_t reg)</td></tr>
<tr class="memitem:aed1bd47654c9fd6cedf4db908a31b3c3"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aed1bd47654c9fd6cedf4db908a31b3c3">reg_is_mmx</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a5a1d70e1fa4c8fb7dc71ff13e57f6b3b"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a5a1d70e1fa4c8fb7dc71ff13e57f6b3b">reg_is_fp</a> (reg_id_t reg)</td></tr>
<tr class="memitem:ae36f78bb9c74e299ea0d469623807356"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ae36f78bb9c74e299ea0d469623807356">reg_is_32bit</a> (reg_id_t reg)</td></tr>
<tr class="memitem:af25fc6d30b3a2fd5010b01e8321b70a8"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#af25fc6d30b3a2fd5010b01e8321b70a8">opnd_is_reg_32bit</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a09b088e600c845776909e02fc7097f8c"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a09b088e600c845776909e02fc7097f8c">reg_is_64bit</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a962f247cc9788c618de75acb7895a142"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a962f247cc9788c618de75acb7895a142">opnd_is_reg_64bit</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a7d1c7cea34276b90917815c18ad7edc2"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a7d1c7cea34276b90917815c18ad7edc2">reg_is_pointer_sized</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a9e132ba3dc1bad4b32a5c61e58ef010f"><td class="memItemLeft" align="right" valign="top">reg_id_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a9e132ba3dc1bad4b32a5c61e58ef010f">reg_to_pointer_sized</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a44667e34cf9b1cde0a7505c85a2800ee"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a44667e34cf9b1cde0a7505c85a2800ee">opnd_is_reg_pointer_sized</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:ae1184de1d13902ad4ac0aeda4242b7b6"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ae1184de1d13902ad4ac0aeda4242b7b6">reg_overlap</a> (reg_id_t r1, reg_id_t r2)</td></tr>
<tr class="memitem:ac1f2d4c9eff29a13269883785cb7e325"><td class="memItemLeft" align="right" valign="top">byte&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ac1f2d4c9eff29a13269883785cb7e325">reg_get_bits</a> (reg_id_t reg)</td></tr>
<tr class="memitem:afd9e2172ccc9943bc1dbd03916744a43"><td class="memItemLeft" align="right" valign="top">opnd_size_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#afd9e2172ccc9943bc1dbd03916744a43">reg_get_size</a> (reg_id_t reg)</td></tr>
<tr class="memitem:a3105684a5aa19fcfb8db45ded15736f1"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a3105684a5aa19fcfb8db45ded15736f1">opnd_uses_reg</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd, reg_id_t reg)</td></tr>
<tr class="memitem:aa99518e779b60b3b5150f7525cb0e4a9"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aa99518e779b60b3b5150f7525cb0e4a9">opnd_set_disp</a> (<a class="el" href="structopnd__t.html">opnd_t</a> *opnd, int disp)</td></tr>
<tr class="memitem:a2e5148e3f5f3799920d29ac800c35e3d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a2e5148e3f5f3799920d29ac800c35e3d">opnd_set_disp_ex</a> (<a class="el" href="structopnd__t.html">opnd_t</a> *opnd, int disp, bool encode_zero_disp, bool force_full_disp, bool disp_short_addr)</td></tr>
<tr class="memitem:a33f97ac94bf4c880c30a2132f15ed2d5"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a33f97ac94bf4c880c30a2132f15ed2d5">opnd_replace_reg</a> (<a class="el" href="structopnd__t.html">opnd_t</a> *opnd, reg_id_t old_reg, reg_id_t new_reg)</td></tr>
<tr class="memitem:adabfafe5e90003ff8e05775beef1f283"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#adabfafe5e90003ff8e05775beef1f283">opnd_same</a> (<a class="el" href="structopnd__t.html">opnd_t</a> op1, <a class="el" href="structopnd__t.html">opnd_t</a> op2)</td></tr>
<tr class="memitem:a9182719a18bb018472c8e8f1a5e8ec4f"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a9182719a18bb018472c8e8f1a5e8ec4f">opnd_same_address</a> (<a class="el" href="structopnd__t.html">opnd_t</a> op1, <a class="el" href="structopnd__t.html">opnd_t</a> op2)</td></tr>
<tr class="memitem:a6429ccee6854e4fd15f8884735d46f1c"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a6429ccee6854e4fd15f8884735d46f1c">opnd_share_reg</a> (<a class="el" href="structopnd__t.html">opnd_t</a> op1, <a class="el" href="structopnd__t.html">opnd_t</a> op2)</td></tr>
<tr class="memitem:a01987e073912f7635a4297b1873fa6de"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a01987e073912f7635a4297b1873fa6de">opnd_defines_use</a> (<a class="el" href="structopnd__t.html">opnd_t</a> def, <a class="el" href="structopnd__t.html">opnd_t</a> use)</td></tr>
<tr class="memitem:a2a0043ae12ecd8dbc9957f8152b0d703"><td class="memItemLeft" align="right" valign="top">uint&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a2a0043ae12ecd8dbc9957f8152b0d703">opnd_size_in_bytes</a> (opnd_size_t size)</td></tr>
<tr class="memitem:ac0dbb90e9aef096dd298a1fc35dffe83"><td class="memItemLeft" align="right" valign="top">opnd_size_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ac0dbb90e9aef096dd298a1fc35dffe83">opnd_size_from_bytes</a> (uint bytes)</td></tr>
<tr class="memitem:ada30617f36545a91ec04faa61aca54e7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#ada30617f36545a91ec04faa61aca54e7">opnd_shrink_to_16_bits</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a493afa708803ec99988e8e0f02a4b554"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a493afa708803ec99988e8e0f02a4b554">opnd_shrink_to_32_bits</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd)</td></tr>
<tr class="memitem:a71b96598edda2662206e87c130d6597e"><td class="memItemLeft" align="right" valign="top">reg_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a71b96598edda2662206e87c130d6597e">reg_get_value</a> (reg_id_t reg, <a class="el" href="dr__defines_8h.html#a5d50a4225e834d67f66438669608e435">dr_mcontext_t</a> *mc)</td></tr>
<tr class="memitem:a2ee18e02a6c4c52b1a83c7ebda0805d6"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a2ee18e02a6c4c52b1a83c7ebda0805d6">reg_get_value_ex</a> (reg_id_t reg, <a class="el" href="dr__defines_8h.html#a5d50a4225e834d67f66438669608e435">dr_mcontext_t</a> *mc, OUT byte *val)</td></tr>
<tr class="memitem:aa89cc8fe8ec09678eeee471bcfcdddd1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#aa89cc8fe8ec09678eeee471bcfcdddd1">reg_set_value</a> (reg_id_t reg, <a class="el" href="dr__defines_8h.html#a5d50a4225e834d67f66438669608e435">dr_mcontext_t</a> *mc, reg_t value)</td></tr>
<tr class="memitem:a8d9ff560c86702c59cd38f9d4cb80477"><td class="memItemLeft" align="right" valign="top">app_pc&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a8d9ff560c86702c59cd38f9d4cb80477">opnd_compute_address</a> (<a class="el" href="structopnd__t.html">opnd_t</a> opnd, <a class="el" href="dr__defines_8h.html#a5d50a4225e834d67f66438669608e435">dr_mcontext_t</a> *mc)</td></tr>
<tr class="memitem:a7f2ed9f0c7db11d7a186f95505f1703a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a7f2ed9f0c7db11d7a186f95505f1703a">opnd_disassemble</a> (void *drcontext, <a class="el" href="structopnd__t.html">opnd_t</a> opnd, file_t outfile)</td></tr>
<tr class="memitem:a5c086d415249d6df5365f889286ec980"><td class="memItemLeft" align="right" valign="top">size_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="dr__ir__opnd_8h.html#a5c086d415249d6df5365f889286ec980">opnd_disassemble_to_buffer</a> (void *drcontext, <a class="el" href="structopnd__t.html">opnd_t</a> opnd, char *buf, size_t bufsz)</td></tr>
</table>
<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
<div class="textblock"><p>Functions and defines to create and manipulate instruction operands. </p>
</div><hr/><h2>Macro Definition Documentation</h2>
<a class="anchor" id="af01db24b9e2a038656f90f1d5230c098"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define DR_REG_LAST_ENUM&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a30d681f080672754d59e4c92eb8110e3">DR_REG_YMM15</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Last value of register enums </p>

</div>
</div>
<a class="anchor" id="a13480b2d07fe53c9292ffaacedcf7231"></a>
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<div class="memproto">
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          <td class="memname">#define DR_REG_LAST_VALID_ENUM&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a30d681f080672754d59e4c92eb8110e3">DR_REG_YMM15</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Last valid register enum value. Note: DR_REG_INVALID is now smaller than this value. </p>

</div>
</div>
<a class="anchor" id="ad553e8814805d1f9b570efdf7a47d896"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define DR_REG_START_16&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a649fcc72a95151540eceed7de932c873">DR_REG_AX</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of 16-bit general register enum values </p>

</div>
</div>
<a class="anchor" id="aca93fb0bd9dd79133bf015b7c15d7229"></a>
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          <td class="memname">#define DR_REG_START_32&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a58aa570736353c817f71fcc400a2d2dc">DR_REG_EAX</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of 32-bit general register enum values </p>

</div>
</div>
<a class="anchor" id="a348d4cc33aa91f7bec586a850499bbbd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_64&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aa5c51b561fd965d340d4cf6266d814b8">DR_REG_RAX</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of 64-bit general register enum values </p>

</div>
</div>
<a class="anchor" id="a81e1aa8fc1dda163c0e39620de24cb7b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_8&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13abc56865077279824d54b6b21a9edaedb">DR_REG_AL</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of 8-bit general register enum values </p>

</div>
</div>
<a class="anchor" id="af9e2d435d6a7bd3d9574f71987bc2653"></a>
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      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_8HL&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13abc56865077279824d54b6b21a9edaedb">DR_REG_AL</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of 8-bit high-low register enum values </p>

</div>
</div>
<a class="anchor" id="a118f2c0b8b2ef31ff3cfce8bf43ad082"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_CR&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a3b6b6f92a247b1bfb3eb8129275211c5">DR_REG_CR0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of control register enum values </p>

</div>
</div>
<a class="anchor" id="ac0ce8f7566d47fde61f419bcf9ac8b6f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_DR&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a12afd3e4492a8046aeef1f1ba5479f95">DR_REG_DR0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of debug register enum values </p>

</div>
</div>
<a class="anchor" id="aa2f7638706a534029356468c35e28349"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_FLOAT&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a7ff61b8acc3f765dbb0dbbf43aeff154">DR_REG_ST0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of floating-point-register enum values </p>

</div>
</div>
<a class="anchor" id="a4ca9d6df48c16d2956a306b382034611"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_GPR&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a12f8bb6c5167165d109aa5fa1301315a">DR_REG_XAX</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of general register enum values </p>

</div>
</div>
<a class="anchor" id="a21a965a72948bf1366a0d9edef188582"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_MMX&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a0bb2aad4eccadd370ab5d45135459fad">DR_REG_MM0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of mmx register enum values </p>

</div>
</div>
<a class="anchor" id="ad9862f4e8a6daa34ace92c2f75b7727a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_SEGMENT&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a919d08fd17cd9ba627e88c8c8cb1397e">DR_SEG_ES</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of segment register enum values </p>

</div>
</div>
<a class="anchor" id="abb2c26e333e07198d5bd98bf414fdb4d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_x64_8&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a861db7ffa318e9ae0ba59c0eb377648c">DR_REG_SPL</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of 8-bit x64-only register enum values </p>

</div>
</div>
<a class="anchor" id="a56f14976648218d6d48ce423f16760c4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_x86_8&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13adafa0b1ee3bee36d2fd6c5cbd5c6ea79">DR_REG_AH</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of 8-bit x86-only register enum values </p>

</div>
</div>
<a class="anchor" id="a9e70a6b298f9a1be8816b62f145fae61"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_XMM&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a4615298b21e7133eeb8786346e970296">DR_REG_XMM0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of xmm register enum values </p>

</div>
</div>
<a class="anchor" id="ad3fa0a9caf2cf2fb82c347b44843e56d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_START_YMM&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a506c32e4da1e93ed469bee48d2746c36">DR_REG_YMM0</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Start of ymm register enum values </p>

</div>
</div>
<a class="anchor" id="ad1bbe340243990fff8758257eee18eb3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_16&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a5f275fb2c1e2ffc985e506238031c389">DR_REG_R15W</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of 16-bit general register enum values </p>

</div>
</div>
<a class="anchor" id="ad2409938ccf74fa8db0457fbee9f5e88"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_32&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a2f1f0ad8ac6362c798af8ec429f14532">DR_REG_R15D</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of 32-bit general register enum values </p>

</div>
</div>
<a class="anchor" id="a2fdaee388ee02fd8b0e1fa556bef1136"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_64&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13af40c522c9dc92ca3e127dc6c49c59a81">DR_REG_R15</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of 64-bit general register enum values </p>

</div>
</div>
<a class="anchor" id="a478694ccbf63b021ff11d6adbd520249"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_8&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a5c3b096d28b0e5a3e94d38f383b22d43">DR_REG_DIL</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of 8-bit general register enum values </p>

</div>
</div>
<a class="anchor" id="a914e5777c887215dc94297335c50b970"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_8HL&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a68fe693aa49db4563f676ad1196798da">DR_REG_BH</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of 8-bit high-low register enum values </p>

</div>
</div>
<a class="anchor" id="a3166c9f50c00c403f13e0025d843e85b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_CR&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a8a3a826c39b63ee447c7ebc46fcd0a64">DR_REG_CR15</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of control register enum values </p>

</div>
</div>
<a class="anchor" id="a078578a811b8f67166a0d26548468697"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_DR&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a89f29c7ce774f35ab307a2dcec374133">DR_REG_DR15</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of debug register enum values </p>

</div>
</div>
<a class="anchor" id="a3c4df606c5a8aeefb46349a49487aba4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_FLOAT&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a0f6c52ab3688ce501eb2ce6c64e05f9d">DR_REG_ST7</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of floating-point-register enum values </p>

</div>
</div>
<a class="anchor" id="a24ceac3fd7c6c0d0d3bda89426e27f3a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_GPR&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13af40c522c9dc92ca3e127dc6c49c59a81">DR_REG_R15</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of general register enum values Number of general registers </p>

</div>
</div>
<a class="anchor" id="a130902890c40315f0979dab79e3b710e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_MMX&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aa1a106a5ddeed1ed3fd0938201860f02">DR_REG_MM7</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of mmx register enum values </p>

</div>
</div>
<a class="anchor" id="a9363b56a0e50b22fb2a55dc2af223c87"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_SEGMENT&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aba960c773accc850f5e245bcf69675fb">DR_SEG_GS</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of segment register enum values </p>

</div>
</div>
<a class="anchor" id="ada32f7b18e997c1596ce851cbd173530"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_x64_8&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a5c3b096d28b0e5a3e94d38f383b22d43">DR_REG_DIL</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Stop of 8-bit x64-only register enum values </p>

</div>
</div>
<a class="anchor" id="ac28597bcf3389872ba7a1d3bd5d0549f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_x86_8&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a68fe693aa49db4563f676ad1196798da">DR_REG_BH</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Stop of 8-bit x86-only register enum values </p>

</div>
</div>
<a class="anchor" id="a51deb7887f669474a53e1cbdd555ef18"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_XMM&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13af2b0dc0ec4e21a0c96772f8bb4938840">DR_REG_XMM15</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of xmm register enum values </p>

</div>
</div>
<a class="anchor" id="a1b6183b82843fc69bbffeae5840cfcee"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_STOP_YMM&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a30d681f080672754d59e4c92eb8110e3">DR_REG_YMM15</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>End of ymm register enum values </p>

</div>
</div>
<a class="anchor" id="a12f8bb6c5167165d109aa5fa1301315a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_XAX&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aa5c51b561fd965d340d4cf6266d814b8">DR_REG_RAX</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Platform-independent way to refer to rax/eax. </p>

</div>
</div>
<a class="anchor" id="ac3af8ac3adf451b4ab10bb4e24fe695e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_XBP&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a2a7f8e7636bc2066a103cacc1171973f">DR_REG_RBP</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Platform-independent way to refer to rbp/ebp. </p>

</div>
</div>
<a class="anchor" id="a22cbc2045400cf933fbf66afbe2b455a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_XBX&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a02092feb3b7da559059ee67eae67b257">DR_REG_RBX</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Platform-independent way to refer to rbx/ebx. </p>

</div>
</div>
<a class="anchor" id="aa47aa41520582cb3ba4eee1fb13e7422"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_XCX&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aa05b6f262667c94bb6e6b1ef454a69b4">DR_REG_RCX</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Platform-independent way to refer to rcx/ecx. </p>

</div>
</div>
<a class="anchor" id="afbead82bd64b12ca809463e35dfabd96"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_XDI&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a1a27364ae96a8795ddcd91239b9625bf">DR_REG_RDI</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Platform-independent way to refer to rdi/edi. </p>

</div>
</div>
<a class="anchor" id="a1d309d3b924d3c1a03097a12961d120c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_XDX&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13acf4384fb8af2fd2e6865ded40e131d5e">DR_REG_RDX</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Platform-independent way to refer to rdx/edx. </p>

</div>
</div>
<a class="anchor" id="a414758053113bc30541c648950e30ffa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_XSI&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13aa01a866894daa9e7f3716a05dd8f79fc">DR_REG_RSI</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Platform-independent way to refer to rsi/esi. </p>

</div>
</div>
<a class="anchor" id="a06b4d3a410d453f25bb74309ef935757"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define DR_REG_XSP&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a39fca1837c5ce7715cbf571669660c13a79c4d3f4b50d5aa74aea84bf88eac7d0">DR_REG_RSP</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Platform-independent way to refer to rsp/esp. </p>

</div>
</div>
<a class="anchor" id="afd7af2c97db706df54e93a703c8993d8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define OPSZ_bound&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a6b22b3dc31990898191d352a02bedb1f">OPSZ_8_short4</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Operand size for bound memory reference. </p>

</div>
</div>
<a class="anchor" id="a505a5cc55d07df68642a384bff1311fd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define OPSZ_call&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#a7398a217ece979ba30b193b2aa3f4e3c">OPSZ_ret</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Operand size for push portion of call. </p>

</div>
</div>
<a class="anchor" id="a7af1cd71dcdc12ee0bd882e0e632770d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define OPSZ_clflush&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a1ae7577a8e73d4a38aa18598de9ba8a6">OPSZ_1</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Operand size for clflush memory reference. </p>

</div>
</div>
<a class="anchor" id="adfdb5621464efafd92c790be4910f792"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define OPSZ_fldenv&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a26719c230384ea132717a65d29b037f2">OPSZ_28_short14</a></td>
        </tr>
      </table>
</div><div class="memdoc">
<p>Operand size for fldenv memory reference. </p>

</div>
</div>
<a class="anchor" id="ab13555485fd05378da3cf406d966240e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define OPSZ_fnsave&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa970ca06e8dc492d880cc8dd657b2f14">OPSZ_108_short94</a></td>
        </tr>
      </table>
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<p>Operand size for fnsave memory reference. </p>

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          <td class="memname">#define OPSZ_fnstenv&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a26719c230384ea132717a65d29b037f2">OPSZ_28_short14</a></td>
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<p>Operand size for fnstenv memory reference. </p>

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          <td class="memname">#define OPSZ_frstor&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa970ca06e8dc492d880cc8dd657b2f14">OPSZ_108_short94</a></td>
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<p>Operand size for frstor memory reference. </p>

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          <td class="memname">#define OPSZ_fxrstor&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a6ee100110eb7730aabf8762c7239a02f">OPSZ_512</a></td>
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<p>Operand size for fxrstor memory reference. </p>

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          <td class="memname">#define OPSZ_fxsave&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a6ee100110eb7730aabf8762c7239a02f">OPSZ_512</a></td>
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<p>Operand size for fxsave memory reference. </p>

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          <td class="memname">#define OPSZ_invlpg&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a5ca16ff95c562237f969f3f1578da995">OPSZ_0</a></td>
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<p>Operand size for invlpg memory reference. </p>

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          <td class="memname">#define OPSZ_lea&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a5ca16ff95c562237f969f3f1578da995">OPSZ_0</a></td>
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<p>Operand size for lea memory reference. </p>

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<a class="anchor" id="ac00f6c2706be7498c21120cf9e721ae7"></a>
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          <td class="memname">#define OPSZ_lgdt&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a></td>
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<p>Operand size for lgdt memory reference. </p>

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<a class="anchor" id="a8ec03cb0036c517b23b553e4462f6456"></a>
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          <td class="memname">#define OPSZ_lidt&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a></td>
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<p>Operand size for lidt memory reference. </p>

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          <td class="memname">#define OPSZ_maskmovdqu&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aa1d772e6c9ef66ff48285c659bec3eca">OPSZ_16</a></td>
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<p>Operand size for maskmovdqu memory reference. </p>

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          <td class="memname">#define OPSZ_maskmovq&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a066a3d6699a61167eb0ba00e529c2e41">OPSZ_8</a></td>
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<p>Operand size for maskmovq memory reference. </p>

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          <td class="memname">#define OPSZ_prefetch&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a1ae7577a8e73d4a38aa18598de9ba8a6">OPSZ_1</a></td>
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<p>Operand size for prefetch memory references. </p>

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          <td class="memname">#define OPSZ_PTR&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a066a3d6699a61167eb0ba00e529c2e41">OPSZ_8</a></td>
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<p>Operand size for pointer values. </p>

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<a class="anchor" id="a7398a217ece979ba30b193b2aa3f4e3c"></a>
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          <td class="memname">#define OPSZ_ret&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4aec5f3627d823c5158599a01e54cc6668">OPSZ_4x8_short2xi8</a></td>
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<p>Operand size for ret instruction. </p>

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<a class="anchor" id="ac3b6d6486ae0825aad79fe1db73ed76b"></a>
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          <td class="memname">#define OPSZ_sgdt&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a></td>
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<p>Operand size for sgdt memory reference. </p>

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<a class="anchor" id="a380f205691106bd9d0a97d92bf13c157"></a>
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          <td class="memname">#define OPSZ_sidt&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c">OPSZ_6x10</a></td>
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<p>Operand size for sidt memory reference. </p>

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<a class="anchor" id="af11e428cd2f68de6cb185384a8fd9713"></a>
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          <td class="memname">#define OPSZ_STACK&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a066a3d6699a61167eb0ba00e529c2e41">OPSZ_8</a></td>
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      </table>
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<p>Operand size for stack push/pop operand sizes. </p>

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<a class="anchor" id="a0cda7955a0d28b070a3fc522d9755323"></a>
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          <td class="memname">#define OPSZ_VARSTACK&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a0119f9bdffad99695b3c2ba9e7588dd5">OPSZ_4x8_short2</a></td>
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<p>Operand size for prefix-varying stack push/pop operand sizes. </p>

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<a class="anchor" id="a6b138a841e72eb3c8340d9aaa16332f5"></a>
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          <td class="memname">#define OPSZ_xlat&#160;&#160;&#160;<a class="el" href="dr__ir__opnd_8h.html#aaf8fd5f0e57d456151c951e0f3715fc4a1ae7577a8e73d4a38aa18598de9ba8a6">OPSZ_1</a></td>
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<p>Operand size for xlat memory reference. </p>

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<hr/><h2>Enumeration Type Documentation</h2>
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          <td class="memname">anonymous enum</td>
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<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a3b7e285b0a732b7da09c0f65a66f7882"></a>DR_REG_NULL</em>&nbsp;</td><td>
<p>Sentinel value indicating no register, for address modes. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aa5c51b561fd965d340d4cf6266d814b8"></a>DR_REG_RAX</em>&nbsp;</td><td>
<p>The "rax" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aa05b6f262667c94bb6e6b1ef454a69b4"></a>DR_REG_RCX</em>&nbsp;</td><td>
<p>The "rcx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13acf4384fb8af2fd2e6865ded40e131d5e"></a>DR_REG_RDX</em>&nbsp;</td><td>
<p>The "rdx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a02092feb3b7da559059ee67eae67b257"></a>DR_REG_RBX</em>&nbsp;</td><td>
<p>The "rbx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a79c4d3f4b50d5aa74aea84bf88eac7d0"></a>DR_REG_RSP</em>&nbsp;</td><td>
<p>The "rsp" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a2a7f8e7636bc2066a103cacc1171973f"></a>DR_REG_RBP</em>&nbsp;</td><td>
<p>The "rbp" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aa01a866894daa9e7f3716a05dd8f79fc"></a>DR_REG_RSI</em>&nbsp;</td><td>
<p>The "rsi" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a1a27364ae96a8795ddcd91239b9625bf"></a>DR_REG_RDI</em>&nbsp;</td><td>
<p>The "rdi" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a6ce9d564068bf72ec43d9162f2119c02"></a>DR_REG_R8</em>&nbsp;</td><td>
<p>The "r8" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a47f7053ccf7bdaf5c778d2391883378d"></a>DR_REG_R9</em>&nbsp;</td><td>
<p>The "r9" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a6047f7e372ce556998d7cb5817a7a5a1"></a>DR_REG_R10</em>&nbsp;</td><td>
<p>The "r10" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5a4e943d15f08c4ddc25fb0527b88c53"></a>DR_REG_R11</em>&nbsp;</td><td>
<p>The "r11" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab872b0fafeb55817f21c95f80ef06c11"></a>DR_REG_R12</em>&nbsp;</td><td>
<p>The "r12" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5b6924937cf9882d7be7a56205ff25d4"></a>DR_REG_R13</em>&nbsp;</td><td>
<p>The "r13" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a16927fccb2fc7be0a63645526d9ea793"></a>DR_REG_R14</em>&nbsp;</td><td>
<p>The "r14" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13af40c522c9dc92ca3e127dc6c49c59a81"></a>DR_REG_R15</em>&nbsp;</td><td>
<p>The "r15" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a58aa570736353c817f71fcc400a2d2dc"></a>DR_REG_EAX</em>&nbsp;</td><td>
<p>The "eax" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5a09a75ede7ccefae6f8ff82bba5bae4"></a>DR_REG_ECX</em>&nbsp;</td><td>
<p>The "ecx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab86ca7bcddcb447aaa3e42e54c294980"></a>DR_REG_EDX</em>&nbsp;</td><td>
<p>The "edx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a9c25504c9114d17fda24e07e2121e888"></a>DR_REG_EBX</em>&nbsp;</td><td>
<p>The "ebx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aef7e5609d413862bbe58a43aa7868281"></a>DR_REG_ESP</em>&nbsp;</td><td>
<p>The "esp" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a10f6ee04809e03dc6d15f5706eb7fff1"></a>DR_REG_EBP</em>&nbsp;</td><td>
<p>The "ebp" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ad18f950de46487e61b838d0245998862"></a>DR_REG_ESI</em>&nbsp;</td><td>
<p>The "esi" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13adaa2f3cfcc4ba64f540aa8aecd15e4b5"></a>DR_REG_EDI</em>&nbsp;</td><td>
<p>The "edi" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ac948fb6247c111a43355a208e63d7eb2"></a>DR_REG_R8D</em>&nbsp;</td><td>
<p>The "r8d" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a104193ac57cd6cf73b5753e8938e47c5"></a>DR_REG_R9D</em>&nbsp;</td><td>
<p>The "r9d" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a7fc2cd5ab301d00ae8bf208583de9740"></a>DR_REG_R10D</em>&nbsp;</td><td>
<p>The "r10d" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aec1268d94642bf6662a58e3a4b6fe783"></a>DR_REG_R11D</em>&nbsp;</td><td>
<p>The "r11d" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ad40565f43b42a773515e91af9759212c"></a>DR_REG_R12D</em>&nbsp;</td><td>
<p>The "r12d" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13af735c064aa13596d28cf35daed61033a"></a>DR_REG_R13D</em>&nbsp;</td><td>
<p>The "r13d" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a0f26f5d9050cda28c9a3a2f93e0940a4"></a>DR_REG_R14D</em>&nbsp;</td><td>
<p>The "r14d" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a2f1f0ad8ac6362c798af8ec429f14532"></a>DR_REG_R15D</em>&nbsp;</td><td>
<p>The "r15d" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a649fcc72a95151540eceed7de932c873"></a>DR_REG_AX</em>&nbsp;</td><td>
<p>The "ax" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aea63157d38dc35dc6e9d36e7065dcb2e"></a>DR_REG_CX</em>&nbsp;</td><td>
<p>The "cx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a6e438d1ee015d3544ade3584e7f191d5"></a>DR_REG_DX</em>&nbsp;</td><td>
<p>The "dx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a0458fb92c04e0270f35322daadd49f8a"></a>DR_REG_BX</em>&nbsp;</td><td>
<p>The "bx" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13acc56139692ee246f01acdbcac55f3ad8"></a>DR_REG_SP</em>&nbsp;</td><td>
<p>The "sp" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13af531be94db548fd19fa15836d0035725"></a>DR_REG_BP</em>&nbsp;</td><td>
<p>The "bp" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5970c370edf10a71f6fd854d259c32d2"></a>DR_REG_SI</em>&nbsp;</td><td>
<p>The "si" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab22932f8f7f70d4bedb3523ab0e2f482"></a>DR_REG_DI</em>&nbsp;</td><td>
<p>The "di" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a4bfdf2fac3dc26376100e195adc9014a"></a>DR_REG_R8W</em>&nbsp;</td><td>
<p>The "r8w" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ad117b44759741032b1001fd71782d190"></a>DR_REG_R9W</em>&nbsp;</td><td>
<p>The "r9w" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab48798bf68a2aed99540db761ea65e07"></a>DR_REG_R10W</em>&nbsp;</td><td>
<p>The "r10w" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a8d84fc622a51d6955bc2731ca9b70838"></a>DR_REG_R11W</em>&nbsp;</td><td>
<p>The "r11w" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13adf558d9b84616baa15027310a84ec08e"></a>DR_REG_R12W</em>&nbsp;</td><td>
<p>The "r12w" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a839c05be022384e6fde26a4d0b34fb11"></a>DR_REG_R13W</em>&nbsp;</td><td>
<p>The "r13w" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13addd70e29cc7f4151753fdd4771e5192a"></a>DR_REG_R14W</em>&nbsp;</td><td>
<p>The "r14w" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5f275fb2c1e2ffc985e506238031c389"></a>DR_REG_R15W</em>&nbsp;</td><td>
<p>The "r15w" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13abc56865077279824d54b6b21a9edaedb"></a>DR_REG_AL</em>&nbsp;</td><td>
<p>The "al" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5b8b4a07d920893d794811b18f3bc8a6"></a>DR_REG_CL</em>&nbsp;</td><td>
<p>The "cl" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ac2e4264d20f59ce7e6c83d41a0976436"></a>DR_REG_DL</em>&nbsp;</td><td>
<p>The "dl" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a3e33e2865d4275fe6aeedaedb2e4a4ad"></a>DR_REG_BL</em>&nbsp;</td><td>
<p>The "bl" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13adafa0b1ee3bee36d2fd6c5cbd5c6ea79"></a>DR_REG_AH</em>&nbsp;</td><td>
<p>The "ah" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ad7b01b71d95c1908190a47698997784c"></a>DR_REG_CH</em>&nbsp;</td><td>
<p>The "ch" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a170f38661a825064376abf0f633e02e0"></a>DR_REG_DH</em>&nbsp;</td><td>
<p>The "dh" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a68fe693aa49db4563f676ad1196798da"></a>DR_REG_BH</em>&nbsp;</td><td>
<p>The "bh" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a318746252f66cf54c6ba7829610ebc41"></a>DR_REG_R8L</em>&nbsp;</td><td>
<p>The "r8l" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a6b1ea9f8ed00afda5648df6abff1157a"></a>DR_REG_R9L</em>&nbsp;</td><td>
<p>The "r9l" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a9a6be7937bbdbe4b7b7915f486e4b075"></a>DR_REG_R10L</em>&nbsp;</td><td>
<p>The "r10l" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13adeb394166c81e3d8ea0ab66e14faab92"></a>DR_REG_R11L</em>&nbsp;</td><td>
<p>The "r11l" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13abeed85ed244cb6f21c86ca58a311e6a0"></a>DR_REG_R12L</em>&nbsp;</td><td>
<p>The "r12l" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a9b108c4dc6dadca230d461356fe5ff47"></a>DR_REG_R13L</em>&nbsp;</td><td>
<p>The "r13l" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aa391aa621dc4079c67932d37635881ec"></a>DR_REG_R14L</em>&nbsp;</td><td>
<p>The "r14l" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13acb32b5298d87ad3c95223b70986dbf8e"></a>DR_REG_R15L</em>&nbsp;</td><td>
<p>The "r15l" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a861db7ffa318e9ae0ba59c0eb377648c"></a>DR_REG_SPL</em>&nbsp;</td><td>
<p>The "spl" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a1c4b15e788699ef9200b44cfd3e15a70"></a>DR_REG_BPL</em>&nbsp;</td><td>
<p>The "bpl" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a12e0f8cf9c21895b273cbbf658d4cdb8"></a>DR_REG_SIL</em>&nbsp;</td><td>
<p>The "sil" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5c3b096d28b0e5a3e94d38f383b22d43"></a>DR_REG_DIL</em>&nbsp;</td><td>
<p>The "dil" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a0bb2aad4eccadd370ab5d45135459fad"></a>DR_REG_MM0</em>&nbsp;</td><td>
<p>The "mm0" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab6de567484af0b954c7fa92958c03787"></a>DR_REG_MM1</em>&nbsp;</td><td>
<p>The "mm1" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13af09dfa439505c404da0300eab361575f"></a>DR_REG_MM2</em>&nbsp;</td><td>
<p>The "mm2" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ae40a88724f7c38098cadd77e2751e715"></a>DR_REG_MM3</em>&nbsp;</td><td>
<p>The "mm3" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ae0de33fc8de1b665545f6af6910d7656"></a>DR_REG_MM4</em>&nbsp;</td><td>
<p>The "mm4" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab6e3750bf44bcab2a9898b88291f44b1"></a>DR_REG_MM5</em>&nbsp;</td><td>
<p>The "mm5" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13af7c9153fb0d54a8e5a0dca13694bfbac"></a>DR_REG_MM6</em>&nbsp;</td><td>
<p>The "mm6" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aa1a106a5ddeed1ed3fd0938201860f02"></a>DR_REG_MM7</em>&nbsp;</td><td>
<p>The "mm7" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a4615298b21e7133eeb8786346e970296"></a>DR_REG_XMM0</em>&nbsp;</td><td>
<p>The "xmm0" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a431578aef63b8ed89421fdb7ffccdfb7"></a>DR_REG_XMM1</em>&nbsp;</td><td>
<p>The "xmm1" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ac44fbdd6d57fae200458a521c2c852ea"></a>DR_REG_XMM2</em>&nbsp;</td><td>
<p>The "xmm2" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a88fd57333ea66af9450fb6c2d14fd38d"></a>DR_REG_XMM3</em>&nbsp;</td><td>
<p>The "xmm3" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab165b4203100a71a349ddfc8d186d4ec"></a>DR_REG_XMM4</em>&nbsp;</td><td>
<p>The "xmm4" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a8a163fadad305acabbab64d82dc2237d"></a>DR_REG_XMM5</em>&nbsp;</td><td>
<p>The "xmm5" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a4feb76719b0d121344210deae9132c2e"></a>DR_REG_XMM6</em>&nbsp;</td><td>
<p>The "xmm6" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a29105717ecb8456ca4d59bdd06ba5b86"></a>DR_REG_XMM7</em>&nbsp;</td><td>
<p>The "xmm7" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a4d420369544f564ab7c06804c700903f"></a>DR_REG_XMM8</em>&nbsp;</td><td>
<p>The "xmm8" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a2e2df4ad09c943c42f9cc24003b72c1a"></a>DR_REG_XMM9</em>&nbsp;</td><td>
<p>The "xmm9" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a02d2dffc83caa2d4e3e10d04231aeeaa"></a>DR_REG_XMM10</em>&nbsp;</td><td>
<p>The "xmm10" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ad4f631eecb2a05df5adcdc0eae355e07"></a>DR_REG_XMM11</em>&nbsp;</td><td>
<p>The "xmm11" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a26c1b609b7548f5cb9cca0390af07913"></a>DR_REG_XMM12</em>&nbsp;</td><td>
<p>The "xmm12" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a188d00b90d6daf5dbc6f413c353c431c"></a>DR_REG_XMM13</em>&nbsp;</td><td>
<p>The "xmm13" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab5cbb5330fc8259cf89d43d8085a7229"></a>DR_REG_XMM14</em>&nbsp;</td><td>
<p>The "xmm14" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13af2b0dc0ec4e21a0c96772f8bb4938840"></a>DR_REG_XMM15</em>&nbsp;</td><td>
<p>The "xmm15" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a7ff61b8acc3f765dbb0dbbf43aeff154"></a>DR_REG_ST0</em>&nbsp;</td><td>
<p>The "st0" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a90fc086cd9943ef2f637d7de46e2c502"></a>DR_REG_ST1</em>&nbsp;</td><td>
<p>The "st1" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a244be1e95e2bfeb371a7540c715d8267"></a>DR_REG_ST2</em>&nbsp;</td><td>
<p>The "st2" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13abb631c13de72e9049b9b382975660ef7"></a>DR_REG_ST3</em>&nbsp;</td><td>
<p>The "st3" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a900ec5bd683489607a2e1ddcf5febdac"></a>DR_REG_ST4</em>&nbsp;</td><td>
<p>The "st4" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ae57de13a8bcf5a88cb20327ee886e82a"></a>DR_REG_ST5</em>&nbsp;</td><td>
<p>The "st5" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a3a648822ae1c1e231d05ab42a4ea8832"></a>DR_REG_ST6</em>&nbsp;</td><td>
<p>The "st6" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a0f6c52ab3688ce501eb2ce6c64e05f9d"></a>DR_REG_ST7</em>&nbsp;</td><td>
<p>The "st7" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a919d08fd17cd9ba627e88c8c8cb1397e"></a>DR_SEG_ES</em>&nbsp;</td><td>
<p>The "es" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a7fc217ce4185051db54a017ca7ec0a51"></a>DR_SEG_CS</em>&nbsp;</td><td>
<p>The "cs" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a7b25ac7f165449bc5a3f0b526289cad1"></a>DR_SEG_SS</em>&nbsp;</td><td>
<p>The "ss" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a7ed8be4b7fbb889a9dd98e11b6f73242"></a>DR_SEG_DS</em>&nbsp;</td><td>
<p>The "ds" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a96f554b9e81693c6f1e29bb68cdaf6fa"></a>DR_SEG_FS</em>&nbsp;</td><td>
<p>The "fs" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aba960c773accc850f5e245bcf69675fb"></a>DR_SEG_GS</em>&nbsp;</td><td>
<p>The "gs" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a12afd3e4492a8046aeef1f1ba5479f95"></a>DR_REG_DR0</em>&nbsp;</td><td>
<p>The "dr0" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5997106510aa2c8a8b0908e2bb2839d9"></a>DR_REG_DR1</em>&nbsp;</td><td>
<p>The "dr1" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a58e299e5a203c7f65db20cc2045a4294"></a>DR_REG_DR2</em>&nbsp;</td><td>
<p>The "dr2" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a5b2f95e7a8f24a25e0844e9cb37e2e06"></a>DR_REG_DR3</em>&nbsp;</td><td>
<p>The "dr3" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a1a9895dfb942a4e1438bd759759ff1df"></a>DR_REG_DR4</em>&nbsp;</td><td>
<p>The "dr4" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ae33d259c9b8bd5024990e8f268d41adf"></a>DR_REG_DR5</em>&nbsp;</td><td>
<p>The "dr5" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a27bf8587cf894530f7e04e65322830b7"></a>DR_REG_DR6</em>&nbsp;</td><td>
<p>The "dr6" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a6af140bc7083695de0c2b2b61344efc2"></a>DR_REG_DR7</em>&nbsp;</td><td>
<p>The "dr7" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a6c567b832d30fa4bdd8dd4cd003df042"></a>DR_REG_DR8</em>&nbsp;</td><td>
<p>The "dr8" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13afc18d7654fc54037da497a829d974ca9"></a>DR_REG_DR9</em>&nbsp;</td><td>
<p>The "dr9" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13adcf7825b9a3b5e9fe6a602c5931a44a9"></a>DR_REG_DR10</em>&nbsp;</td><td>
<p>The "dr10" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a212cdf4abeaeec5dbce57cd9b429628f"></a>DR_REG_DR11</em>&nbsp;</td><td>
<p>The "dr11" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a899c58c62dace6e5858fd8cadaada2c8"></a>DR_REG_DR12</em>&nbsp;</td><td>
<p>The "dr12" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13acb934cabe9cd3b188b638c6c17f6cfa8"></a>DR_REG_DR13</em>&nbsp;</td><td>
<p>The "dr13" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a52d5b46d08b686a719821a1ac927bac8"></a>DR_REG_DR14</em>&nbsp;</td><td>
<p>The "dr14" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a89f29c7ce774f35ab307a2dcec374133"></a>DR_REG_DR15</em>&nbsp;</td><td>
<p>The "dr15" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a3b6b6f92a247b1bfb3eb8129275211c5"></a>DR_REG_CR0</em>&nbsp;</td><td>
<p>The "cr0" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a86b9e72f7a735b92bf497fbd5515dcba"></a>DR_REG_CR1</em>&nbsp;</td><td>
<p>The "cr1" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aba7af08dcaafc2dbe3c98ba52cb1f3b2"></a>DR_REG_CR2</em>&nbsp;</td><td>
<p>The "cr2" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a21c3267961f5abb9ab5887f0bd70581d"></a>DR_REG_CR3</em>&nbsp;</td><td>
<p>The "cr3" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ae2f361f257ca972ac1e02771d98cfc4e"></a>DR_REG_CR4</em>&nbsp;</td><td>
<p>The "cr4" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13abb5ed4626f8c59bcaf3f42700a3d8fa2"></a>DR_REG_CR5</em>&nbsp;</td><td>
<p>The "cr5" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a33e5f8f41e4001147cbbdc991300a6d5"></a>DR_REG_CR6</em>&nbsp;</td><td>
<p>The "cr6" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a2bb88c4f1e662daa53dbd75b07c8895c"></a>DR_REG_CR7</em>&nbsp;</td><td>
<p>The "cr7" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a77bcc2c3a49a858d0b77118b89466412"></a>DR_REG_CR8</em>&nbsp;</td><td>
<p>The "cr8" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a103a98c7eb4d976fa117fed3578dfe81"></a>DR_REG_CR9</em>&nbsp;</td><td>
<p>The "cr9" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13af9a5ba2c19c637a69d5cf25f73e5d34f"></a>DR_REG_CR10</em>&nbsp;</td><td>
<p>The "cr10" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a6b654a966b48977c3687c2b24f7fe8ef"></a>DR_REG_CR11</em>&nbsp;</td><td>
<p>The "cr11" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a457d424c43f5a32b4e8ddc5e1344b086"></a>DR_REG_CR12</em>&nbsp;</td><td>
<p>The "cr12" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a7493f68f4c93f46b7a0032885b0701f4"></a>DR_REG_CR13</em>&nbsp;</td><td>
<p>The "cr13" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a7deb6444d23c983c69cd4067781d6be8"></a>DR_REG_CR14</em>&nbsp;</td><td>
<p>The "cr14" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a8a3a826c39b63ee447c7ebc46fcd0a64"></a>DR_REG_CR15</em>&nbsp;</td><td>
<p>The "cr15" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13af627e9b7e65af958771933dba270783b"></a>DR_REG_INVALID</em>&nbsp;</td><td>
<p>Sentinel value indicating an invalid register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a506c32e4da1e93ed469bee48d2746c36"></a>DR_REG_YMM0</em>&nbsp;</td><td>
<p>The "ymm0" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ac6bfad04cc3881630749998d37cc8b94"></a>DR_REG_YMM1</em>&nbsp;</td><td>
<p>The "ymm1" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ad6f63ec6b3fc6fd85b1f61fac5afea8c"></a>DR_REG_YMM2</em>&nbsp;</td><td>
<p>The "ymm2" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a1c1e1c5da3d90aa0defada496eb8f5e8"></a>DR_REG_YMM3</em>&nbsp;</td><td>
<p>The "ymm3" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13afce2a84d7b7296826a0015074d49a875"></a>DR_REG_YMM4</em>&nbsp;</td><td>
<p>The "ymm4" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ab71fb800029282debea33210753b4a8a"></a>DR_REG_YMM5</em>&nbsp;</td><td>
<p>The "ymm5" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a1ce86c2f2d9e753d50ad0d9ba38bdd15"></a>DR_REG_YMM6</em>&nbsp;</td><td>
<p>The "ymm6" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13adc8ee6513706d60ce50ef527aa270896"></a>DR_REG_YMM7</em>&nbsp;</td><td>
<p>The "ymm7" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a52c18153e2decc9e3197f7f35ca1a5fa"></a>DR_REG_YMM8</em>&nbsp;</td><td>
<p>The "ymm8" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ae7556ce24f531722623da3dedabf0cbb"></a>DR_REG_YMM9</em>&nbsp;</td><td>
<p>The "ymm9" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a60f4862d1094ad97111a6dec83a59cd9"></a>DR_REG_YMM10</em>&nbsp;</td><td>
<p>The "ymm10" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a636d90b537b7bc3359ad49469eab847f"></a>DR_REG_YMM11</em>&nbsp;</td><td>
<p>The "ymm11" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13ad186d80221df365f693a5d5f10455d53"></a>DR_REG_YMM12</em>&nbsp;</td><td>
<p>The "ymm12" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13aae6c9c9daf4daa70b10637881e97c0c6"></a>DR_REG_YMM13</em>&nbsp;</td><td>
<p>The "ymm13" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a60ab04ccb23565254ee97fffd83fe92e"></a>DR_REG_YMM14</em>&nbsp;</td><td>
<p>The "ymm14" register. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="a39fca1837c5ce7715cbf571669660c13a30d681f080672754d59e4c92eb8110e3"></a>DR_REG_YMM15</em>&nbsp;</td><td>
<p>The "ymm15" register. </p>
</td></tr>
</table>
</dd>
</dl>

</div>
</div>
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          <td class="memname">anonymous enum</td>
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<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4ad8ebfb0c9725d4de8dc822fe6e0434a4"></a>OPSZ_NA</em>&nbsp;</td><td>
<p>Sentinel value: not a valid size. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a5ca16ff95c562237f969f3f1578da995"></a>OPSZ_0</em>&nbsp;</td><td>
<p>Intel 'm': "sizeless": used for both start addresses (lea, invlpg) and implicit constants (rol, fldl2e, etc.) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a1ae7577a8e73d4a38aa18598de9ba8a6"></a>OPSZ_1</em>&nbsp;</td><td>
<p>Intel 'b': 1 byte </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a17ae2b57438dc78b74918634536ab8ec"></a>OPSZ_2</em>&nbsp;</td><td>
<p>Intel 'w': 2 bytes </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a0ccef0d75b3f473bf275388804c8b85c"></a>OPSZ_4</em>&nbsp;</td><td>
<p>Intel 'd','si': 4 bytes </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a0bd061af35fa7349ae8f49f52c70d353"></a>OPSZ_6</em>&nbsp;</td><td>
<p>Intel 'p','s': 6 bytes </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a066a3d6699a61167eb0ba00e529c2e41"></a>OPSZ_8</em>&nbsp;</td><td>
<p>Intel 'q','pi': 8 bytes </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4ad77bb391958eb41218d362142f19c071"></a>OPSZ_10</em>&nbsp;</td><td>
<p>Intel 's' 64-bit, or double extended precision floating point (latter used by fld, fstp, fbld, fbstp) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4aa1d772e6c9ef66ff48285c659bec3eca"></a>OPSZ_16</em>&nbsp;</td><td>
<p>Intel 'dq','ps','pd','ss','sd', or AMD 'o': 16 bytes </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a518e12d87392b8b0fcb87bbc37d5e43d"></a>OPSZ_14</em>&nbsp;</td><td>
<p>FPU operating environment with short data size (fldenv, fnstenv) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a3a1817fe7db80f134788fd82643f1aae"></a>OPSZ_28</em>&nbsp;</td><td>
<p>FPU operating environment with normal data size (fldenv, fnstenv) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a4a3e5ca13e5d2e4efedef6d5e1d4e79c"></a>OPSZ_94</em>&nbsp;</td><td>
<p>FPU state with short data size (fnsave, frstor) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a69e3b06a69484ded9cdc60bd0cdb37fe"></a>OPSZ_108</em>&nbsp;</td><td>
<p>FPU state with normal data size (fnsave, frstor) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a6ee100110eb7730aabf8762c7239a02f"></a>OPSZ_512</em>&nbsp;</td><td>
<p>FPU, MMX, XMM state (fxsave, fxrstor) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a903faaf86532c743c799845eb11eff7e"></a>OPSZ_2_short1</em>&nbsp;</td><td>
<p>The following sizes (OPSZ_*_short*) vary according to the cs segment and the operand size prefix. This IR assumes that the cs segment is set to the default operand size. The operand size prefix then functions to shrink the size. The IR does not explicitly mark the prefix; rather, a shortened size is requested in the operands themselves, with the IR adding the prefix at encode time. Normally the fixed sizes above should be used rather than these variable sizes, which are used internally by the IR and should only be externally specified when building an operand in order to be flexible and allow other operands to decide the size for the instruction (the prefix applies to the entire instruction). Intel 'c': 2/1 bytes ("2/1" means 2 bytes normally, but if another operand requests a short size then this size can accommodate by shifting to its short size, which is 1 byte). </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a7b7c9306312252995d6e0634ee0a3caa"></a>OPSZ_4_short2</em>&nbsp;</td><td>
<p>Intel 'z': 4/2 bytes </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a32ada6d380c77e31381cbad6f2dd2718"></a>OPSZ_4_rex8_short2</em>&nbsp;</td><td>
<p>Intel 'v': 8/4/2 bytes </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4ad623004d7c3a3b723815c429c9cc0355"></a>OPSZ_4_rex8</em>&nbsp;</td><td>
<p>Intel 'd/q' (like 'v' but never 2 bytes) or 'y'. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4aa4d243486345db5568617b738388c0de"></a>OPSZ_6_irex10_short4</em>&nbsp;</td><td>
<p>Intel 'p': On Intel processors this is 10/6/4 bytes for segment selector + address. On AMD processors this is 6/4 bytes for segment selector + address (rex is ignored). </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4ab85e1e4770430376365d9ccdc4edbeef"></a>OPSZ_8_short2</em>&nbsp;</td><td>
<p>partially resolved 4x8_short2 </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a6b22b3dc31990898191d352a02bedb1f"></a>OPSZ_8_short4</em>&nbsp;</td><td>
<p>Intel 'a': pair of 4_short2 (bound) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a26719c230384ea132717a65d29b037f2"></a>OPSZ_28_short14</em>&nbsp;</td><td>
<p>FPU operating env variable data size (fldenv, fnstenv) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4aa970ca06e8dc492d880cc8dd657b2f14"></a>OPSZ_108_short94</em>&nbsp;</td><td>
<p>FPU state with variable data size (fnsave, frstor) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a9d969185f0b397e78c06ab0b45f07a00"></a>OPSZ_4x8</em>&nbsp;</td><td>
<pre class="fragment">                                                                                                                               Varies by 32-bit versus 64-bit processor mode.   Full register size with no variation by prefix.
</pre><p> Used for control and debug register moves. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a878d2304c24913e0739e0dcdab04be0c"></a>OPSZ_6x10</em>&nbsp;</td><td>
<p>Intel 's': 6-byte (10-byte for 64-bit mode) table base + limit </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a0119f9bdffad99695b3c2ba9e7588dd5"></a>OPSZ_4x8_short2</em>&nbsp;</td><td>
<p>Stack operands not only vary by operand size specifications but also by 32-bit versus 64-bit processor mode. Intel 'v'/'d64' for stack operations. Also 64-bit address-size specified operands, which are short4 rather than short2 in 64-bit mode (but short2 in 32-bit mode). Note that this IR does not distinguish extra stack operations performed by OP_enter w/ non-zero immed. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4aec5f3627d823c5158599a01e54cc6668"></a>OPSZ_4x8_short2xi8</em>&nbsp;</td><td>
<p>Intel 'f64': 4_short2 for 32-bit, 8_short2 for 64-bit AMD, always 8 for 64-bit Intel </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a674723f76cae47df43261656d550b0b1"></a>OPSZ_4_short2xi4</em>&nbsp;</td><td>
<p>Intel 'f64': 4_short2 for 32-bit or 64-bit AMD, always 4 for 64-bit Intel </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a01324b1c6672d657c931c192140a3c52"></a>OPSZ_1_reg4</em>&nbsp;</td><td>
<p>The following 3 sizes differ based on whether the modrm chooses a register or memory. Intel Rd/Mb: zero-extends if reg; used by pextrb </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4ad4c71f8b85b6d29bfab5979cfe665e3d"></a>OPSZ_2_reg4</em>&nbsp;</td><td>
<p>Intel Rd/Mw: zero-extends if reg; used by pextrw </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4ac5ca3360d331fded45ee1cefbc6a7447"></a>OPSZ_4_reg16</em>&nbsp;</td><td>
<p>Intel Udq/Md: 4 bytes of xmm or 4 bytes of memory; used by insertps. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4ab3abe67788f31af3804456b54ce4fe3f"></a>OPSZ_xsave</em>&nbsp;</td><td>
<p>Size is &gt; 512 bytes: use cpuid to determine. Used for FPU, MMX, XMM, etc. state by xsave and xrstor. </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a4f9af8f5df4e4ad8a5790a96405c1ae8"></a>OPSZ_12</em>&nbsp;</td><td>
<p>12 bytes: 32-bit iret </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4abcfb8f7f5225a98205186f02ee24c25d"></a>OPSZ_32</em>&nbsp;</td><td>
<p>32 bytes: pusha/popa Also Intel 'qq','pd','ps','x': 32 bytes (256 bits) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4aabba0c8aa7f8e2c7e6558a3067c958c4"></a>OPSZ_40</em>&nbsp;</td><td>
<p>40 bytes: 64-bit iret </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a0b33dc779b6e35a692933392845748d3"></a>OPSZ_32_short16</em>&nbsp;</td><td>
<p>unresolved pusha/popa </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4abea75bfe53a3c81f12ebc38e382378aa"></a>OPSZ_8_rex16</em>&nbsp;</td><td>
<p>cmpxcgh8b/cmpxchg16b </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4acf7f69fbb6d4eb3b898590fba55348b7"></a>OPSZ_8_rex16_short4</em>&nbsp;</td><td>
<p>Intel 'v' * 2 (far call/ret) </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4af2ed43be9c2201e06c76a1b36f79920f"></a>OPSZ_12_rex40_short6</em>&nbsp;</td><td>
<p>unresolved iret </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4aeff79665bf0fa144556f2964a498bc94"></a>OPSZ_16_vex32</em>&nbsp;</td><td>
<p>16 or 32 bytes depending on VEX.L (AMD/Intel 'x'). </p>
</td></tr>
<tr><td valign="top"><em><a class="anchor" id="aaf8fd5f0e57d456151c951e0f3715fc4a860c730e78eac07dc1b57377fad5887c"></a>OPSZ_15</em>&nbsp;</td><td>
<p>All but one byte of an xmm register (used by OP_vpinsrb). </p>
</td></tr>
</table>
</dd>
</dl>

</div>
</div>
<hr/><h2>Function Documentation</h2>
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          <td class="memname">const char* get_register_name </td>
          <td>(</td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>reg</em></td><td>)</td>
          <td></td>
        </tr>
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<p>Assumes that <code>reg</code> is a DR_REG_ 32-bit register constant. Returns the string name for <code>reg</code>. </p>

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          <td class="memname">app_pc opnd_compute_address </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="dr__defines_8h.html#a5d50a4225e834d67f66438669608e435">dr_mcontext_t</a> *&#160;</td>
          <td class="paramname"><em>mc</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Returns the effective address of <code>opnd</code>, computed using the passed-in register values. If <code>opnd</code> is a far address, ignores that aspect except for TLS references on Windows (fs: for 32-bit, gs: for 64-bit) or typical fs: or gs: references on Linux. For far addresses the calling thread's segment selector is used. <code>mc-&gt;flags</code> must include DR_MC_CONTROL and DR_MC_INTEGER.</p>
<dl class="section note"><dt>Note:</dt><dd>This routine does not support vector addressing (via VSIB, introduced in AVX2). Use <a class="el" href="dr__ir__instr_8h.html#aa13ec559a17ab70816f80de784e5632f">instr_compute_address()</a>, <a class="el" href="dr__ir__instr_8h.html#aa04322a189dd7f17ab245594e02cc6a8">instr_compute_address_ex()</a>, or <a class="el" href="dr__ir__instr_8h.html#a25107e1fb5a49de3c627b70acc7b2eef">instr_compute_address_ex_pos()</a> instead. </dd></dl>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_create_abs_addr </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
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          <td class="paramtype">opnd_size_t&#160;</td>
          <td class="paramname"><em>data_size</em>&#160;</td>
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<p>Returns a memory reference operand that refers to the address <code>addr</code>. The operand has data size <code>data_size</code> (must be a OPSZ_ constant).</p>
<p>If <code>addr</code> &lt;= 2^32 (which is always true in 32-bit mode), this routine is equivalent to opnd_create_base_disp(DR_REG_NULL, DR_REG_NULL, 0, (int)addr, data_size).</p>
<p>Otherwise, this routine creates a separate operand type with an absolute 64-bit memory address. Such an operand can only be guaranteed to be encodable in absolute form as a load or store from or to the rax (or eax) register. It will automatically be converted to a pc-relative operand (as though <a class="el" href="dr__ir__opnd_8h.html#a429f69f7bc430cf278b5702818b25fcc">opnd_create_rel_addr()</a> had been called) if it is used in any other way. </p>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_create_base_disp </td>
          <td>(</td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>base_reg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>index_reg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>scale</em>, </td>
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          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>disp</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">opnd_size_t&#160;</td>
          <td class="paramname"><em>data_size</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Returns a memory reference operand that refers to the address:</p>
<ul>
<li>disp(base_reg, index_reg, scale)</li>
</ul>
<p>or, in other words,</p>
<ul>
<li>base_reg + index_reg*scale + disp</li>
</ul>
<p>The operand has data size data_size (must be a OPSZ_ constant). Both <code>base_reg</code> and <code>index_reg</code> must be DR_REG_ constants. <code>scale</code> must be either 1, 2, 4, or 8. </p>

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          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>base_reg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>index_reg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>scale</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>disp</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">opnd_size_t&#160;</td>
          <td class="paramname"><em>size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>encode_zero_disp</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>force_full_disp</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>disp_short_addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Returns a memory reference operand that refers to the address:</p>
<ul>
<li>disp(base_reg, index_reg, scale)</li>
</ul>
<p>or, in other words,</p>
<ul>
<li>base_reg + index_reg*scale + disp</li>
</ul>
<p>The operand has data size <code>data_size</code> (must be a OPSZ_ constant). Both <code>base_reg</code> and <code>index_reg</code> must be DR_REG_ constants. <code>scale</code> must be either 1, 2, 4, or 8. Gives control over encoding optimizations:</p>
<ol type="1">
<li>If <code>encode_zero_disp</code>, a zero value for disp will not be omitted;</li>
<li>If <code>force_full_disp</code>, a small value for disp will not occupy only one byte.</li>
<li>If <code>disp_short_addr</code>, short (16-bit for 32-bit mode, 32-bit for 64-bit mode) addressing will be used (note that this normally only needs to be specified for an absolute address; otherwise, simply use the desired short registers for base and/or index).</li>
</ol>
<p>(Both of those are false when using <a class="el" href="dr__ir__opnd_8h.html#a009d49c1c9dec11da5b4f4b644bd9c72">opnd_create_base_disp()</a>). </p>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_create_far_abs_addr </td>
          <td>(</td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>seg</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
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          <td></td>
          <td class="paramtype">opnd_size_t&#160;</td>
          <td class="paramname"><em>data_size</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
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<p>Returns a memory reference operand that refers to the address <code>seg:</code> <code>addr</code>. The operand has data size <code>data_size</code> (must be a OPSZ_ constant).</p>
<p>If <code>addr</code> &lt;= 2^32 (which is always true in 32-bit mode), this routine is equivalent to opnd_create_far_base_disp(seg, DR_REG_NULL, DR_REG_NULL, 0, (int)addr, data_size).</p>
<p>Otherwise, this routine creates a separate operand type with an absolute 64-bit memory address. Such an operand can only be guaranteed to be encodable in absolute form as a load or store from or to the rax (or eax) register. It will automatically be converted to a pc-relative operand (as though <a class="el" href="dr__ir__opnd_8h.html#a5378f9a33c968e32ac7ebc9acb8db3bb">opnd_create_far_rel_addr()</a> had been called) if it is used in any other way. </p>

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          <td>(</td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>seg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>base_reg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>index_reg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>scale</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>disp</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">opnd_size_t&#160;</td>
          <td class="paramname"><em>data_size</em>&#160;</td>
        </tr>
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          <td></td>
          <td>)</td>
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<p>Returns a far memory reference operand that refers to the address:</p>
<ul>
<li>seg : disp(base_reg, index_reg, scale)</li>
</ul>
<p>or, in other words,</p>
<ul>
<li>seg : base_reg + index_reg*scale + disp</li>
</ul>
<p>The operand has data size <code>data_size</code> (must be a OPSZ_ constant). <code>seg</code> must be a DR_SEG_ constant. Both <code>base_reg</code> and <code>index_reg</code> must be DR_REG_ constants. <code>scale</code> must be either 1, 2, 4, or 8. </p>

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          <td>(</td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>seg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>base_reg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>index_reg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>scale</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">int&#160;</td>
          <td class="paramname"><em>disp</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">opnd_size_t&#160;</td>
          <td class="paramname"><em>size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>encode_zero_disp</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>force_full_disp</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>disp_short_addr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Returns a far memory reference operand that refers to the address:</p>
<ul>
<li>seg : disp(base_reg, index_reg, scale)</li>
</ul>
<p>or, in other words,</p>
<ul>
<li>seg : base_reg + index_reg*scale + disp</li>
</ul>
<p>The operand has data size <code>data_size</code> (must be a OPSZ_ constant). <code>seg</code> must be a DR_SEG_ constant. Both <code>base_reg</code> and <code>index_reg</code> must be DR_REG_ constants. scale must be either 1, 2, 4, or 8. Gives control over encoding optimizations:</p>
<ol type="1">
<li>If <code>encode_zero_disp</code>, a zero value for disp will not be omitted;</li>
<li>If <code>force_full_disp</code>, a small value for disp will not occupy only one byte.</li>
<li>If <code>disp_short_addr</code>, short (16-bit for 32-bit mode, 32-bit for 64-bit mode) addressing will be used (note that this normally only needs to be specified for an absolute address; otherwise, simply use the desired short registers for base and/or index).</li>
</ol>
<p>(All of these are false when using <a class="el" href="dr__ir__opnd_8h.html#ad40dc03947985fe2ce948377b3a630ce">opnd_create_far_base_disp()</a>). </p>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_create_far_instr </td>
          <td>(</td>
          <td class="paramtype">ushort&#160;</td>
          <td class="paramname"><em>seg_selector</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="structinstr__t.html">instr_t</a> *&#160;</td>
          <td class="paramname"><em>instr</em>&#160;</td>
        </tr>
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          <td></td>
          <td>)</td>
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<p>Returns a far <a class="el" href="structinstr__t.html">instr_t</a> pointer address with value <code>seg_selector:instr</code>. <code>seg_selector</code> is a segment selector, not a DR_SEG_ constant. </p>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_create_far_pc </td>
          <td>(</td>
          <td class="paramtype">ushort&#160;</td>
          <td class="paramname"><em>seg_selector</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">app_pc&#160;</td>
          <td class="paramname"><em>pc</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Returns a far program address operand with value <code>seg_selector:pc</code>. <code>seg_selector</code> is a segment selector, not a DR_SEG_ constant. </p>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_create_far_rel_addr </td>
          <td>(</td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>seg</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">opnd_size_t&#160;</td>
          <td class="paramname"><em>data_size</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Returns a memory reference operand that refers to the address <code>seg</code> : <code>addr</code>, but will be encoded as a pc-relative address. It is up to the caller to ensure that the resulting address is reachable via a 32-bit signed displacement from the next instruction at emit time.</p>
<p>DR guarantees that all of its code caches, all client libraries and Extensions (though not copies of system libraries), and all client memory allocated through <a class="el" href="dr__tools_8h.html#a4274226adda06339e247e4a311abdd9b">dr_thread_alloc()</a>, <a class="el" href="dr__tools_8h.html#a60faa40f7e8c819c34fd25cb367c5473">dr_global_alloc()</a>, <a class="el" href="dr__tools_8h.html#ac32b5be072876c25a832d510efeba6e4">dr_nonheap_alloc()</a>, or <a class="el" href="dr__tools_8h.html#a3cfff0780cf83588e3d71da552490eb7">dr_custom_alloc()</a> with <a class="el" href="dr__tools_8h.html#abb7e20e83f7b8e1b65428e45c8ab4211ab33a2e990410bf314bdebe6a25aa06e1">DR_ALLOC_CACHE_REACHABLE</a>, can reach each other with a 32-bit displacement. Thus, any normally-allocated data or any static data or code in a client library is guaranteed to be reachable from code cache code. Memory allocated through system libraries (including malloc, operator new, and HeapAlloc) is not guaranteed to be reachable: only memory directly allocated via DR's API. The runtime option -reachable_heap can be used to guarantee that all memory is reachable.</p>
<p>If <code>addr</code> is not pc-reachable at encoding time and this operand is used in a load or store to or from the rax (or eax) register, an absolute form will be used (as though <a class="el" href="dr__ir__opnd_8h.html#a8716c716b3589b75e887a86f782433be">opnd_create_far_abs_addr()</a> had been called).</p>
<p>The operand has data size <code>data_size</code> (must be a OPSZ_ constant).</p>
<p>To represent a 32-bit address (i.e., what an address size prefix indicates), simply zero out the top 32 bits of the address before passing it to this routine.</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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          <td>(</td>
          <td class="paramtype">float&#160;</td>
          <td class="paramname"><em>f</em></td><td>)</td>
          <td></td>
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<p>Returns an immediate float operand with value <code>f</code>. The caller's code should use <a class="el" href="dr__proc_8h.html#a4a11c9d5d127ce126562ad35b4d165dd">proc_save_fpstate()</a> or be inside a clean call that has requested to preserve the floating-point state. </p>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_create_immed_int </td>
          <td>(</td>
          <td class="paramtype">ptr_int_t&#160;</td>
          <td class="paramname"><em>i</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">opnd_size_t&#160;</td>
          <td class="paramname"><em>data_size</em>&#160;</td>
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<p>Returns an immediate integer operand with value <code>i</code> and size <code>data_size</code>; <code>data_size</code> must be a OPSZ_ constant. </p>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_create_instr </td>
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          <td class="paramtype"><a class="el" href="structinstr__t.html">instr_t</a> *&#160;</td>
          <td class="paramname"><em>instr</em></td><td>)</td>
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<p>Returns an operand whose value will be the encoded address of <code>instr</code>. This operand can be used as an immediate integer or as a direct call or jump target. Its size is always <a class="el" href="dr__ir__opnd_8h.html#a992970f92f717142180ea31fe5eb2493">OPSZ_PTR</a>. </p>

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          <td>(</td>
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          <td class="paramname"><em>instr</em>, </td>
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          <td class="paramname"><em>size</em>, </td>
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<p>Returns an operand whose value will be the encoded address of <code>instr</code>. This operand can be used as an immediate integer or as a direct call or jump target. Its size is the specified <code>size</code>. Its value can be optionally right-shifted by <code>shift</code> from the encoded address. </p>

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          <td class="paramname"><em>instr</em>, </td>
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<p>Returns a memory reference operand whose value will be the encoded address of <code>instr</code> plus the 16-bit displacement <code>disp</code>. For 32-bit mode, it will be encoded just like an absolute address (<a class="el" href="dr__ir__opnd_8h.html#a6c4e5d5376ce4dc1ba7081119d97a16d">opnd_create_abs_addr()</a>); for 64-bit mode, it will be encoded just like a pc-relative address (<a class="el" href="dr__ir__opnd_8h.html#a429f69f7bc430cf278b5702818b25fcc">opnd_create_rel_addr()</a>). This operand can be used anywhere a regular memory operand can be used. Its size is <code>data_size</code>.</p>
<dl class="section note"><dt>Note:</dt><dd>This operand will return false to <a class="el" href="dr__ir__opnd_8h.html#aa278662a54e9df9de5f06c30e53d7596">opnd_is_instr()</a>, <a class="el" href="dr__ir__opnd_8h.html#a17c7a1b3e5a6eecdfdb5bf69cdf2ecd4">opnd_is_rel_addr()</a>, and <a class="el" href="dr__ir__opnd_8h.html#a22bbf7d42f7ff2011970294e70176caf">opnd_is_abs_addr()</a>. It is a separate type. </dd></dl>

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<p>Returns an empty operand. </p>

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          <td class="paramname"><em>pc</em></td><td>)</td>
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<p>Returns a program address operand with value <code>pc</code>. </p>

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          <td class="paramname"><em>r</em></td><td>)</td>
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<p>Returns a register operand (<code>r</code> must be a DR_REG_ constant). </p>

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<p>Returns a register operand corresponding to a part of the multimedia register represented by the DR_REG_ constant <code>r</code>, which must be an mmx, xmm, or ymm register. For partial general-purpose registers, use the appropriate sub-register name with <a class="el" href="dr__ir__opnd_8h.html#a0714576ebc35cf7efe2855126ad716e1">opnd_create_reg()</a> instead. </p>

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<p>Returns a memory reference operand that refers to the address <code>addr</code>, but will be encoded as a pc-relative address. At emit time, if <code>addr</code> is out of reach of a 32-bit signed displacement from the next instruction, encoding will fail.</p>
<p>DR guarantees that all of its code caches, all client libraries and Extensions (though not copies of system libraries), and all client memory allocated through <a class="el" href="dr__tools_8h.html#a4274226adda06339e247e4a311abdd9b">dr_thread_alloc()</a>, <a class="el" href="dr__tools_8h.html#a60faa40f7e8c819c34fd25cb367c5473">dr_global_alloc()</a>, <a class="el" href="dr__tools_8h.html#ac32b5be072876c25a832d510efeba6e4">dr_nonheap_alloc()</a>, or <a class="el" href="dr__tools_8h.html#a3cfff0780cf83588e3d71da552490eb7">dr_custom_alloc()</a> with <a class="el" href="dr__tools_8h.html#abb7e20e83f7b8e1b65428e45c8ab4211ab33a2e990410bf314bdebe6a25aa06e1">DR_ALLOC_CACHE_REACHABLE</a>, can reach each other with a 32-bit displacement. Thus, any normally-allocated data or any static data or code in a client library is guaranteed to be reachable from code cache code. Memory allocated through system libraries (including malloc, operator new, and HeapAlloc) is not guaranteed to be reachable: only memory directly allocated via DR's API. The runtime option -reachable_heap can be used to guarantee that all memory is reachable.</p>
<p>If <code>addr</code> is not pc-reachable at encoding time and this operand is used in a load or store to or from the rax (or eax) register, an absolute form will be used (as though <a class="el" href="dr__ir__opnd_8h.html#a6c4e5d5376ce4dc1ba7081119d97a16d">opnd_create_abs_addr()</a> had been called).</p>
<p>The operand has data size data_size (must be a OPSZ_ constant).</p>
<p>To represent a 32-bit address (i.e., what an address size prefix indicates), simply zero out the top 32 bits of the address before passing it to this routine.</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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<p>Returns true iff <code>def</code>, considered as a write, affects <code>use</code>. Is conservative, so if both <code>def</code> and <code>use</code> are memory references, will return true unless it can disambiguate them based on their registers and displacement. </p>

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<p>Prints the operand <code>opnd</code> to file <code>outfile</code>. The default is to use AT&amp;T-style syntax, unless the <a class="el" href="using.html#op_syntax_intel">-syntax_intel</a> runtime option is specified. </p>

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          <td class="paramtype">char *&#160;</td>
          <td class="paramname"><em>buf</em>, </td>
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          <td class="paramtype">size_t&#160;</td>
          <td class="paramname"><em>bufsz</em>&#160;</td>
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<p>Prints the operand <code>opnd</code> to the buffer <code>buf</code>. Always null-terminates, and will not print more than <code>bufsz</code> characters, which includes the final null character. Returns the number of characters printed, not including the final null. The default is to use AT&amp;T-style syntax, unless the <a class="el" href="using.html#op_syntax_intel">-syntax_intel</a> runtime option is specified. </p>

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<p>Assumes <code>opnd</code> is a (near or far) absolute or pc-relative memory reference, or a base+disp memory reference with no base or index register. Returns <code>opnd's</code> absolute address (which will be pc-relativized on encoding for pc-relative memory references). </p>

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<p>Assumes <code>opnd</code> is a (near or far) base+disp memory reference. Returns the base register (a DR_REG_ constant). </p>

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<p>Assumes <code>opnd</code> is a (near or far) base+disp memory reference. Returns the displacement. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is an immediate float and returns its value. The caller's code should use <a class="el" href="dr__proc_8h.html#a4a11c9d5d127ce126562ad35b4d165dd">proc_save_fpstate()</a> or be inside a clean call that has requested to preserve the floating-point state. </p>

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<p>Assumes opnd is an immediate integer, returns its value. </p>

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<p>Assumes <code>opnd</code> is a (near or far) base+disp memory reference. Returns the index register (a DR_REG_ constant). </p>

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          <td>(</td>
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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is an <a class="el" href="structinstr__t.html">instr_t</a> (near, far, or memory) operand and returns its value. </p>

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<p>Assumes <code>opnd</code> is a memory instr operand. Returns its displacement. </p>

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          <td>(</td>
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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is a (near or far) program address, returns its value. </p>

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<p>Assumes <code>opnd</code> is a register operand. Returns the register it refers to (a DR_REG_ constant). </p>

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          <td class="paramname"><em>opnd</em>, </td>
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<p>Used in conjunction with <a class="el" href="dr__ir__opnd_8h.html#aeb508e0926cc8bcba006da1e0bc8138b">opnd_num_regs_used()</a>, this routine can be used to iterate through all registers used by <code>opnd</code>. The index values begin with 0 and proceed through opnd_num_regs_used(opnd)-1. </p>

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          <td class="memname">int opnd_get_scale </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is a (near or far) base+disp memory reference. Returns the scale. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is a (near or far) memory reference of any type. Returns <code>opnd's</code> segment (a DR_SEG_ constant), or DR_REG_NULL if it is a near memory reference. </p>

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          <td class="memname">ushort opnd_get_segment_selector </td>
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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is a far program address. Returns <code>opnd's</code> segment, a segment selector (not a DR_SEG_ constant). </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is a near <a class="el" href="structinstr__t.html">instr_t</a> operand and returns its shift value. </p>

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          <td class="memname">opnd_size_t opnd_get_size </td>
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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Return the data size of <code>opnd</code> as a OPSZ_ constant. Returns OPSZ_NA if <code>opnd</code> does not have a valid size. </p>
<dl class="section note"><dt>Note:</dt><dd>A register operand may have a size smaller than the full size of its DR_REG_* register specifier. </dd></dl>

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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a (near or far) absolute address operand. Returns true for both base-disp operands with no base or index and 64-bit non-base-disp absolute address operands. </p>

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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a (near or far) base+disp memory reference operand. </p>

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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is a (near or far) base+disp memory reference; returns whether encode_zero_disp has been specified for <code>opnd</code>. </p>

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          <td class="memname">bool opnd_is_disp_force_full </td>
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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is a (near or far) base+disp memory reference; returns whether force_full_disp has been specified for <code>opnd</code>. </p>

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          <td class="memname">bool opnd_is_disp_short_addr </td>
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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Assumes <code>opnd</code> is a (near or far) base+disp memory reference; returns whether disp_short_addr has been specified for <code>opnd</code>. </p>

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          <td class="memname">bool opnd_is_far_abs_addr </td>
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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a far absolute address operand. Returns true for both base-disp operands with no base or index and 64-bit non-base-disp absolute address operands. </p>

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          <td class="memname">INSTR_INLINE bool opnd_is_far_base_disp </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a far base+disp memory reference operand. </p>

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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a far <a class="el" href="structinstr__t.html">instr_t</a> pointer address operand. </p>

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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a far memory reference operand of any type: base-disp, absolute address, or pc-relative address. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a far program address operand. </p>

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          <td class="memname">INSTR_INLINE bool opnd_is_far_rel_addr </td>
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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a far pc-relative memory reference operand.</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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          <td class="memname">INSTR_INLINE bool opnd_is_immed </td>
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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is an immediate (integer or float) operand. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is an immediate float operand. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is an immediate integer operand. </p>

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          <td class="memname">INSTR_INLINE bool opnd_is_instr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a (near or far) <a class="el" href="structinstr__t.html">instr_t</a> pointer address operand. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a memory reference to an <a class="el" href="structinstr__t.html">instr_t</a> address operand. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a (near or far) memory reference operand of any type: base-disp, absolute address, or pc-relative address.</p>
<p>This routine (along with all other opnd_ routines) does consider multi-byte nops that use addressing operands, or the <a class="el" href="dr__ir__opcodes_8h.html#aae05225933a42f81e7c4a9fb286596f9a8e5722f2fffd08c1e03efa408a6a0f55">OP_lea</a> instruction's source operand, to be memory references: i.e., it only considers whether the operand calculates an address. Use <a class="el" href="dr__ir__instr_8h.html#ae408fe229bea0aa800cddb6b911c0e94">instr_reads_memory()</a> to operate on a higher semantic level and rule out these corner cases. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a near (i.e., default segment) absolute address operand. Returns true for both base-disp operands with no base or index and 64-bit non-base-disp absolute address operands. </p>

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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a near (i.e., default segment) base+disp memory reference operand. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a near <a class="el" href="structinstr__t.html">instr_t</a> pointer address operand. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a near memory reference operand of any type: base-disp, absolute address, or pc-relative address. </p>

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<p>Returns true iff <code>opnd</code> is a near (i.e., default segment) program address operand. </p>

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          <td class="memname">INSTR_INLINE bool opnd_is_near_rel_addr </td>
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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a near (i.e., default segment) pc-relative memory reference operand.</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is an empty operand. </p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a (near or far) program address operand. </p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a register operand. </p>

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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a register operand that refers to a 32-bit general-purpose register. </p>

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          <td>(</td>
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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a register operand that refers to a 64-bit general-purpose register. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a partial multimedia register operand. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a register operand that refers to a pointer-sized general-purpose register. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> is a (near or far) pc-relative memory reference operand.</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns true iff <code>opnd</code> uses vector indexing via a VSIB byte. This memory addressing form was introduced in Intel AVX2. </p>

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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Returns the number of registers referred to by <code>opnd</code>. This will only be non-zero for register operands and memory references. </p>

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          <td class="paramname"><em>opnd</em>, </td>
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          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>old_reg</em>, </td>
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          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>new_reg</em>&#160;</td>
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<p>Assumes that both <code>old_reg</code> and <code>new_reg</code> are DR_REG_ constants. Replaces all occurrences of <code>old_reg</code> in <code>*opnd</code> with <code>new_reg</code>. </p>

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          <td class="paramname"><em>op1</em>, </td>
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          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>op2</em>&#160;</td>
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<p>Returns true iff <code>op1</code> and <code>op2</code> are indistinguishable. If either uses variable operand sizes, the default size is assumed. </p>

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          <td class="paramname"><em>op1</em>, </td>
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<p>Returns true iff <code>op1</code> and <code>op2</code> are both memory references and they are indistinguishable, ignoring data size. </p>

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          <td class="paramname"><em>opnd</em>, </td>
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          <td class="paramname"><em>disp</em>&#160;</td>
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<p>Set the displacement of a memory reference operand <code>opnd</code> to <code>disp</code>. </p>

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          <td class="paramname"><em>opnd</em>, </td>
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          <td class="paramname"><em>force_full_disp</em>, </td>
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<p>Set the displacement and encoding controls of a memory reference operand:</p>
<ul>
<li>If <code>encode_zero_disp</code>, a zero value for <code>disp</code> will not be omitted;</li>
<li>If <code>force_full_disp</code>, a small value for <code>disp</code> will not occupy only one byte.</li>
</ul>
<ol type="1">
<li>If <code>disp_short_addr</code>, short (16-bit for 32-bit mode, 32-bit for 64-bit mode) addressing will be used (note that this normally only needs to be specified for an absolute address; otherwise, simply use the desired short registers for base and/or index). </li>
</ol>

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          <td class="paramname"><em>opnd</em>, </td>
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<p>Sets the data size of <code>opnd</code>. Assumes <code>opnd</code> is an immediate integer, a memory reference, or an <a class="el" href="structinstr__t.html">instr_t</a> pointer address operand. </p>

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          <td class="paramname"><em>op1</em>, </td>
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          <td class="paramname"><em>op2</em>&#160;</td>
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<p>Returns true iff there exists some register that is referred to (directly or overlapping) by both <code>op1</code> and <code>op2</code>. </p>

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          <td class="memname"><a class="el" href="structopnd__t.html">opnd_t</a> opnd_shrink_to_16_bits </td>
          <td>(</td>
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          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Shrinks all 32-bit registers in <code>opnd</code> to their 16-bit versions. Also shrinks the size of immediate integers and memory references from OPSZ_4 to OPSZ_2. </p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="structopnd__t.html">opnd_t</a>&#160;</td>
          <td class="paramname"><em>opnd</em></td><td>)</td>
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<p>Shrinks all 64-bit registers in <code>opnd</code> to their 32-bit versions. Also shrinks the size of immediate integers and memory references from OPSZ_8 to OPSZ_4.</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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          <td class="paramname"><em>bytes</em></td><td>)</td>
          <td></td>
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<p>Returns the appropriate OPSZ_ constant for the given number of bytes. Returns OPSZ_NA if there is no such constant. The intended use case is something like "opnd_size_in_bytes(sizeof(foo))" for integer/pointer types. This routine returns simple single-size types and will not return complex/variable size types. </p>

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          <td class="paramname"><em>size</em></td><td>)</td>
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<p>Assumes <code>size</code> is a OPSZ_ or a DR_REG_ constant. If <code>size</code> is a DR_REG_ constant, first calls reg_get_size(<code>size</code>) to get a OPSZ_ constant that assumes the entire register is used. Returns the number of bytes the OPSZ_ constant represents. If OPSZ_ is a variable-sized size, returns the default size, which may or may not match the actual size decided up on at encoding time (that final size depends on other operands). </p>

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          <td class="paramname"><em>opnd</em>, </td>
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          <td class="paramname"><em>reg</em>&#160;</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff <code>opnd</code> refers to reg directly or refers to a register that overlaps <code>reg</code> (e.g., DR_REG_AX overlaps DR_REG_EAX). </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ 32-bit register constant. Returns the 16-bit version of <code>reg</code>. </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ 32-bit register constant. Returns the 64-bit version of <code>reg</code>.</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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<p>Assumes that <code>reg</code> is a DR_REG_ 32-bit register constant. Returns the 8-bit version of <code>reg</code> (the least significant byte: DR_REG_AL instead of DR_REG_AH if passed DR_REG_EAX, e.g.). For 32-bit DR builds, returns DR_REG_NULL if passed DR_REG_ESP, DR_REG_EBP, DR_REG_ESI, or DR_REG_EDI. </p>

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          <td class="paramname"><em>reg</em>, </td>
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<p>Assumes that <code>reg</code> is a DR_REG_ 32-bit register constant. If <code>sz</code> == OPSZ_2, returns the 16-bit version of <code>reg</code>. For 64-bit versions of this library, if <code>sz</code> == OPSZ_8, returns the 64-bit version of <code>reg</code>. Returns <code>DR_REG_NULL</code> when trying to get the 8-bit subregister of <code>DR_REG_ESI</code>, <code>DR_REG_EDI</code>, <code>DR_REG_EBP</code>, or <code>DR_REG_ESP</code> in 32-bit mode.</p>
<dl class="deprecated"><dt><b><a class="el" href="deprecated.html#_deprecated000005">Deprecated:</a></b></dt><dd>Prefer <a class="el" href="dr__ir__opnd_8h.html#adccf1dfd3ec95b71a8a0b205cf48da7a">reg_resize_to_opsz()</a> which is more general. </dd></dl>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ 64-bit register constant. Returns the 32-bit version of <code>reg</code>.</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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          <td>(</td>
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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns <code>reg's</code> representation as 3 bits in a modrm byte (the 3 bits are the lower-order bits in the return value). </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns the OPSZ_ constant corresponding to the register size. Returns OPSZ_NA if reg is not a DR_REG_ constant. </p>

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          <td>(</td>
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          <td class="paramtype"><a class="el" href="dr__defines_8h.html#a5d50a4225e834d67f66438669608e435">dr_mcontext_t</a> *&#160;</td>
          <td class="paramname"><em>mc</em>&#160;</td>
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<p>Returns the value of the register <code>reg</code>, selected from the passed-in register values. Supports only general-purpose registers. <code>mc-&gt;flags</code> must include DR_MC_CONTROL and DR_MC_INTEGER. </p>

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          <td class="paramname"><em>reg</em>, </td>
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          <td class="paramkey"></td>
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          <td class="paramtype"><a class="el" href="dr__defines_8h.html#a5d50a4225e834d67f66438669608e435">dr_mcontext_t</a> *&#160;</td>
          <td class="paramname"><em>mc</em>, </td>
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          <td class="paramtype">OUT byte *&#160;</td>
          <td class="paramname"><em>val</em>&#160;</td>
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          <td>)</td>
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<p>Returns the value of the register <code>reg</code> as stored in <code>mc</code>, or for an mmx register as stored in the physical register. Up to sizeof(dr_ymm_t) bytes will be written to <code>val</code>.</p>
<p>This routine does not support floating-point registers.</p>
<dl class="section note"><dt>Note:</dt><dd><code>mc-&gt;flags</code> must include the appropriate flag for the requested register. </dd></dl>

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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to a 32-bit general-purpose register. </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to a 64-bit general-purpose register. </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Returns true iff <code>reg</code> refers to an extended register only available in 64-bit mode and not in 32-bit mode (e.g., R8-R15, XMM8-XMM15, etc.)</p>
<dl class="section note"><dt>Note:</dt><dd>For 64-bit DR builds only. </dd></dl>

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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to a floating-point register. </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to a General Purpose Register, i.e., rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, or a subset. </p>

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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to an mmx (64-bit) register. </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to a pointer-sized general-purpose register. </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to a segment (i.e., it's really a DR_SEG_ constant). </p>

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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to an xmm (128-bit SSE/SSE2) register or a ymm (256-bit multimedia) register. </p>

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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ constant. Returns true iff it refers to a ymm (256-bit multimedia) register. </p>

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          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>r1</em>, </td>
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          <td></td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>r2</em>&#160;</td>
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          <td>)</td>
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<p>Assumes that <code>r1</code> and <code>r2</code> are both DR_REG_ constants. Returns true iff <code>r1's</code> register overlaps <code>r2's</code> register (e.g., if <code>r1</code> == DR_REG_AX and <code>r2</code> == DR_REG_EAX). </p>

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<p>Assumes that <code>reg</code> is a DR_REG_ register constant. If reg is used as part of the calling convention, returns which parameter ordinal it matches (0-based); otherwise, returns -1. </p>

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          <td class="paramname"><em>reg</em>, </td>
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          <td class="paramname"><em>sz</em>&#160;</td>
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<p>Given a general-purpose register of any size, returns a register in the same class of the given size. For example, given <code>DR_REG_AX</code> or <code>DR_REG_RAX</code> and <code>OPSZ_1</code>, this routine will return <code>DR_REG_AL</code>. Returns <code>DR_REG_NULL</code> when trying to get the 8-bit subregister of <code>DR_REG_ESI</code>, <code>DR_REG_EDI</code>, <code>DR_REG_EBP</code>, or <code>DR_REG_ESP</code> in 32-bit mode. For 64-bit versions of this library, if <code>sz</code> == OPSZ_8, returns the 64-bit version of <code>reg</code>. </p>

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          <td class="memname">void reg_set_value </td>
          <td>(</td>
          <td class="paramtype">reg_id_t&#160;</td>
          <td class="paramname"><em>reg</em>, </td>
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          <td class="paramtype"><a class="el" href="dr__defines_8h.html#a5d50a4225e834d67f66438669608e435">dr_mcontext_t</a> *&#160;</td>
          <td class="paramname"><em>mc</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">reg_t&#160;</td>
          <td class="paramname"><em>value</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>Sets the register <code>reg</code> in the passed in mcontext <code>mc</code> to <code>value</code>. <code>mc-&gt;flags</code> must include DR_MC_CONTROL and DR_MC_INTEGER. </p>
<dl class="section note"><dt>Note:</dt><dd>Current release is limited to setting pointer-sized registers only (no sub-registers, and no non-general-purpose registers). </dd></dl>

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          <td class="memname">reg_id_t reg_to_pointer_sized </td>
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          <td class="paramname"><em>reg</em></td><td>)</td>
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<p>Assumes that <code>reg</code> is a DR_REG_ 32-bit register constant. Returns the pointer-sized version of <code>reg</code>. </p>

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